GPU Systolic Array Matrix Accelerator for AI Throughput
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Solution Overview
Problem
Current graphics processing units (GPUs) face challenges in efficiently performing matrix multiplication operations, which are key to artificial intelligence workloads, due to limitations in throughput and parallel processing efficiency.
Innovation Solution
Implementing a systolic array matrix accelerator within the GPU architecture to enhance matrix multiplication operations, utilizing a systolic array programming model for cluster-based matrix operations and asynchronous DMA programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional GPU architecture is used for matrix multiplication, then device complexity is maintained at current levels, but throughput and parallel processing efficiency are insufficient for AI workloads
Solution Approach 1:
The GPU architecture is segmented by introducing a dedicated systolic array matrix accelerator unit separate from traditional CUDA cores. This accelerator is further divided into multiple systolic arrays that can be configured for different matrix operation sizes, allowing specialized high-throughput processing while maintaining the existing GPU architecture for other tasks.
Solution Approach 2:
The systolic array accelerator is designed with configurable dimensions and modes that allow it to perform multiple matrix operation types (GEMM, GEMV, etc.) and support various precision formats (FP32, FP16, INT8). This multi-functionality enables a single accelerator unit to handle diverse AI workload requirements without requiring separate specialized hardware for each operation type.
2Productivity
If systolic array accelerator is integrated into GPU, then parallel processing efficiency for matrix operations is improved, but device complexity increases
Solution Approach 1:
The systolic array accelerator is nested within the existing GPU architecture as a dedicated unit that can be integrated into the streaming multiprocessor structure. The accelerator itself contains nested systolic arrays that can be further subdivided into smaller processing elements, creating a hierarchical structure that maximizes parallel processing efficiency while organizing complexity in a manageable nested format.
3Productivity
If systolic array programming model is implemented, then matrix operation throughput is enhanced, but ease of operation decreases due to programming complexity
Solution Approach 1:
A programming model intermediary layer is introduced that translates high-level matrix operation specifications into detailed systolic array configuration instructions. This intermediary handles the complexity of array dimension configuration, data layout transformation, and operation scheduling, allowing developers to program using familiar linear algebra operations while the intermediary manages the underlying systolic array complexity.
4Productivity
If asynchronous DMA programming is used, then data transfer efficiency is improved, but device complexity increases
Solution Approach 1:
Data is pre-loaded into the systolic array accelerator's on-chip memory buffers before matrix operations begin through asynchronous DMA transfers. This preliminary action allows data to be staged in advance without blocking the main computation pipeline, and the DMA operations are configured with predetermined patterns that simplify the programming interface while maximizing transfer efficiency.
Data Source
AI summary
One embodiment provides a graphics processor comprising a base die including a plurality of chiplet sockets and a plurality of chiplets coupled with the plurality of chiplet sockets, at least one of the plurality of chiplets including a plurality of processing elements and a matrix accelerator coupled with the plurality of processing elements, the matrix accelerator having circuitry to perform a matrix multiply accumulate operation on matrix data having a tiled memory layout.