3D GPU Memory Access via Control Die and Through-Silicon-Vias
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Solution Overview
Problem
Current 3D graphics processing units face challenges in memory design and interface efficiency due to high data processing demands, requiring improved memory access techniques to enhance performance.
Innovation Solution
A technique is implemented for accessing memory in an accelerated processing device coupled to stacked memory dies, where a control die coordinates operations by identifying local and non-local memory access requests, using through-silicon-vias for direct local access and a distributed cache fabric and interconnect bus for non-local access, optimizing memory access latency and size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory size is increased to handle high data processing demands, then memory capacity improves, but memory access latency increases
Solution Approach 1:
The patent segments memory into local memory regions coupled directly to execution units and remote memory regions accessed through the memory bus. This segmentation allows frequently accessed data to be stored locally for immediate access while less frequently accessed data resides in remote memory, thereby increasing overall memory capacity without significantly increasing access latency for critical data.
Solution Approach 2:
The patent implements local memory with direct coupling to execution units, providing low-latency access for local data operations. Meanwhile, remote memory provides extended capacity through the memory bus. This local quality differentiation ensures that time-critical operations access fast local memory while utilizing the larger remote memory capacity when needed.
2Productivity
If memory bandwidth is increased to handle high data processing demands, then data throughput improves, but power consumption increases
Solution Approach 1:
The patent segments memory access paths into local direct-access paths and remote bus-based paths. By segmenting data access this way, the system can handle high throughput for local data operations with minimal power consumption while using the power-intensive memory bus only when additional capacity is required, thus improving overall productivity without proportionally increasing power usage.
3Productivity
If memory interface complexity is increased to optimize access patterns, then memory performance improves, but device complexity increases
Solution Approach 1:
The patent segments the memory interface into simple local access logic directly at execution units and a separate memory bus controller for remote access. This segmentation allows each component to remain relatively simple while the coordinated system achieves high memory performance through the combination of direct local access and managed remote access.
Data Source
AI summary
A technique for accessing memory in an accelerated processing device coupled to stacked memory dies is provided herein. The technique includes receiving a memory access request from an execution unit and identifying whether the memory access request corresponds to memory cells of the stacked dies that are considered local to the execution unit or non-local. For local accesses, the access is made “directly”, that is, without using a bus. A control die coordinates operations for such local accesses, activating particular through-silicon-vias associated with the memory cells that include the data for the access. Non-local accesses are made via a distributed cache fabric and an interconnect bus in the control die. Various other features and details are provided below.