GPU Memory Expansion via Cross-Chip Interconnectors
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Solution Overview
Problem
Existing graphics memory expansion methods for high-performance GPUs on discrete graphics cards occupy physical space and pose challenges to wiring, and the graphics memory controllers are unable to increase the upper limit of memory capacity without altering the hardware architecture.
Innovation Solution
A GPU processor system that includes a set of GPU chips with irremovable graphics memory controllers and cross-chip interconnectors, connected to separate graphics memory expansions via non-QPI interconnection buses, allowing access to additional graphics memories without altering the existing graphics memory controllers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If separate graphics memory expansions are added to high-performance GPUs, then graphics memory capacity is increased, but hardware structure alteration and wiring complexity increase
Solution Approach 1:
The system segments the graphics memory into two independent parts: integrated graphics memory (H1j) that is irremovably coupled to the GPU chip, and separate graphics memory expansions (H2i) that are added independently through dedicated expansion interfaces. This segmentation allows memory capacity expansion without requiring changes to the core GPU hardware structure.
Solution Approach 2:
The cross-chip interconnector is designed with multi-functionality, serving both as an interface for separate graphics memory expansions and as an interconnection interface for GPU chip sets. This universal interface reduces wiring complexity by consolidating multiple functions into a single standardized connection.
2Device complexity
If graphics memory is irremovably coupled to the GPU chip, then memory capacity is limited, but hardware structure simplicity is maintained
Solution Approach 1:
The graphics memory system is divided into two independent segments: the integrated graphics memory (H1j) that maintains hardware simplicity by being irremovably coupled, and separate graphics memory expansions (H2i) that provide capacity scalability. Both segments operate independently with their own controllers, allowing capacity expansion without compromising the simplicity of the core GPU structure.
3Adaptability or versatility
If internal memory is shared between CPU and GPU, then memory capacity utilization is improved, but access speed and bandwidth are reduced
Solution Approach 1:
The memory system is segmented into shared internal memory (for CPU-GPU capacity utilization) and separate graphics memory expansions (for GPU-dedicated high-speed access). The separate expansions provide dedicated high-bandwidth pathways through cross-chip interconnectors, ensuring that GPU-intensive operations maintain high access speeds while the shared internal memory provides overall capacity utilization.
Solution Approach 2:
The cross-chip interconnector acts as an intermediary that provides dedicated high-speed access pathways between the GPU and separate graphics memory expansions, bypassing the shared internal memory controller. This intermediary mechanism ensures that time-critical GPU operations access memory through optimized dedicated channels while still allowing the shared memory to be utilized for less time-sensitive operations.
Data Source
AI summary
The system comprises a set of N GPU chips and a graphics memory H1j on a graphics card on which the GPU chip Cj is mounted. Cj includes a graphics memory controller MC1j and cross-chip interconnectors. The system further comprises graphics memory expansions. The graphics memory expansion Ei comprises a graphics memory controller MC2i, a graphics memory H2i and a cross-chip interconnector SACi. The q(j)-th cross-chip interconnector FACq(j)j and SACi are interconnected using a non-QPI interconnection bus. MC1j is unable to control access to H2i, and MC2i is unable to control access to H1j. Any processor other than Cj has no access to MC2i, or the processor is given access to MC2i exclusively through FACjq(j) and SACi if the processor has access to MC2i. Separate graphics memories special for GPU are increased in the system, without altering the hardware architectures of MC1j and GPU.