GPU Memory Instruction Fault Checking via Master-Slave Requests
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Solution Overview
Problem
Graphics Processing Units (GPUs) face challenges in fault tolerance, particularly in preventing Silent Data Corruption (SDC) in GPGPU code, where traditional fault detection mechanisms like ECC incur significant area overhead, and there is a need for a low-cost fault detection mechanism to protect both on-chip memories and logic, especially in power-efficient designs and critical market segments.
Innovation Solution
A system and method that converts slave requests to dummy operations, modifies the memory arbiter to issue N master and N slave global operations per cycle, uses slave requests for error checking, and employs parity information to verify master and slave operations and data, ensuring error detection and correction through redundant multithreading techniques like Inter-WaveFront and Inter-Compute Unit RMT.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional fault detection mechanisms such as ECC are used, then fault detection capability is improved, but area overhead increases significantly
Solution Approach 1:
The patent implements fault detection by creating a redundant copy of the memory operation through master-slave instruction pairs. The slave instruction executes the same memory operation as the master instruction, and the results are compared to detect faults. This copying approach provides fault detection capability without requiring traditional ECC overhead, as the redundancy is achieved through instruction-level replication rather than bit-level checksums.
Solution Approach 2:
The system uses the GPU's own existing computational resources (ALUs, memory interfaces) to perform the fault detection function. By utilizing the slave instruction execution and result comparison within the existing architecture, the system achieves fault detection without adding dedicated ECC hardware, thereby avoiding significant area overhead while maintaining reliability.
2Reliability
If fault protection mechanisms are added to protect on-chip memories and logic, then reliability is improved, but device complexity increases
Solution Approach 1:
The master and slave instructions serve multiple functions: the master instruction performs the primary computation while the slave instruction simultaneously serves as both a computational unit and a fault detection reference. The comparison logic reuses existing data paths and ALU outputs, making the fault protection mechanism integrated into the normal execution flow rather than a separate additive layer, thus avoiding excessive complexity.
3Reliability
If slave requests are converted to dummy operations for error checking, then fault detection is improved, but memory bandwidth utilization decreases
Solution Approach 1:
The patent merges the fault detection function with the existing memory request handling infrastructure. Slave requests are processed through the same memory arbitration and issue logic as master requests, utilizing existing data paths and comparison units. The dummy operation conversion is implemented at the instruction scheduling level, allowing the memory subsystem to handle both master and slave requests efficiently without requiring dedicated error-checking memory paths, thereby minimizing impact on bandwidth utilization.
Data Source
AI summary
A system and method for protecting memory instructions against faults are described. The system and method include converting the slave instructions to dummy operations, modifying memory arbiter to issue up to N master and N slave global/shared memory instructions per cycle, sending master memory requests to memory system, using slave requests for error checking, entering master requests to the GM/LM FIFO, storing slave requests in a register, and comparing the entered master requests with the stored slave requests.