Multi-Process Service Memory Limiting for GPU Resource Interference

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Solution Overview

Problem

The increasing power of parallel processing units (PPUs) like GPUs leads to underutilization due to ineffective resource management by CPU schedulers, resulting in interference between independent CPU processes utilizing PPU resources.

Innovation Solution

A multi-process service (MPS) is introduced to manage and enforce memory limits on thread groups executed by GPUs, allowing for better resource allocation and utilization by sharing scheduling resources among processes, thereby preventing resource interference.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple independent CPU processes are used to utilize GPU resources, then PPU computing power utilization increases, but resource interference between processes occurs

Engineering Contradiction:
ImprovePPU computing power utilizationVSAvoidresource interference between processes
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent introduces a scheduler as an intermediary component that manages and coordinates resource allocation between multiple CPU processes and the PPU. The scheduler acts as a mediator that prevents direct interference between processes by controlling access to shared PPU resources through a centralized scheduling mechanism, thereby maintaining high utilization while eliminating harmful interference.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The scheduler is designed as a universal resource management system that handles multiple types of resources (memory, compute units, execution contexts) and serves multiple CPU processes simultaneously. This multi-functional scheduler consolidates resource management capabilities into a single system that can dynamically allocate and manage diverse PPU resources for different processes without requiring separate management mechanisms.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If memory limits are enforced on thread groups, then resource allocation efficiency improves, but system complexity increases

Engineering Contradiction:
Improveresource allocation efficiencyVSAvoidmemory management system complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements memory limits by changing the parameter of memory allocation size for thread groups. The scheduler dynamically adjusts memory allocation parameters based on process requirements and system state, enforcing limits through parameter control rather than structural modifications. This approach improves allocation efficiency by preventing memory exhaustion while adding minimal complexity through parameter management.

Inventive Principle:
Principle #35Parameter changes

3Ease of operation

If CPU schedulers manage PPU resources directly, then ease of operation is maintained, but resource management effectiveness deteriorates

Engineering Contradiction:
Improvescheduler operation simplicityVSAvoidresource management effectiveness
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent introduces a specialized PPU scheduler as an intermediary between the CPU scheduler and PPU resources. This intermediary scheduler handles the complex task of PPU resource management, allowing the CPU scheduler to maintain its simple operation while the specialized scheduler ensures effective and reliable resource allocation. The intermediary translates high-level CPU scheduling decisions into detailed PPU resource allocation without exposing complexity to the CPU scheduler.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20230185611A1Application programming interface to limit memory
Publication Date: 2023.06.15 NVIDIA CORP
  • US20230185611A1 patent drawing
  • US20230185611A1 patent drawing
  • US20230185611A1 patent drawing

AI summary

Apparatuses, systems, and techniques to limit memory during execution of one or more kernels and/or thread groups during PPU execution. In at least one embodiment, a process indicates a memory limit for one or more kernels and/or thread groups to a parallel processing library, and said parallel processing library restricts memory allocation for said one or more kernels and/or thread groups according to said memory limit.