GPU Memory Instruction Lockstep Checking for Low-Cost Fault Detection
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Solution Overview
Problem
Graphics Processing Units (GPUs) face challenges in fault tolerance, particularly in preventing Silent Data Corruption (SDC) in GPGPU code, where traditional fault detection mechanisms like ECC incur significant area overhead, and there is a need for a low-cost fault detection mechanism to protect both on-chip memories and logic, especially in power-efficient near-threshold operations.
Innovation Solution
A system and method that converts slave requests to dummy operations, modifies the memory arbiter to issue N master and N slave global operations per cycle, uses slave requests for error checking, and employs parity information for error detection, allowing master and slave instructions to be executed in lockstep with error checking and replay mechanisms to ensure data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional fault detection mechanisms such as ECC are used in GPU memory systems, then reliability is improved, but area overhead increases significantly
Solution Approach 1:
The patent implements a master-slave copy mechanism where slave memory requests are created as redundant copies of master requests. These slave requests are processed in parallel and used for error detection through comparison, providing fault detection capability without requiring traditional ECC overhead. The slave requests are converted to dummy operations that mirror the master request sequence and are validated against the master results.
Solution Approach 2:
The patent changes the operational parameters of the memory system by introducing dual-issue capability where the memory arbiter can issue both master and slave requests simultaneously. This parameter change allows the system to achieve error detection through operational redundancy rather than through additional correction codes, thereby maintaining area efficiency while improving reliability.
2Use of energy by moving object
If GPU operates at lower voltage for power efficiency, then energy consumption is reduced, but fault susceptibility increases
Solution Approach 1:
The patent implements error detection mechanisms that prepare and validate memory operations before they complete. By issuing slave requests in advance and comparing results beforehand, the system can detect faults that may occur during low-voltage operation, providing a cushion against Silent Data Corruption without requiring higher operating voltages.
Solution Approach 2:
The patent establishes a feedback loop where slave memory request results are compared against master request results. This feedback mechanism allows the system to detect and correct errors that occur during low-voltage operation, maintaining reliability despite reduced power margins. The comparison logic provides continuous monitoring that compensates for increased fault susceptibility at lower voltages.
3Reliability
If master and slave instructions are executed in lockstep with error checking, then data integrity is improved, but processing time increases
Solution Approach 1:
The patent maintains continuous useful action by executing slave requests in parallel with master requests rather than sequentially. Both request types are issued simultaneously by the memory arbiter and processed concurrently, allowing error checking to occur without halting the normal memory operation flow. This continuity ensures that data integrity verification does not significantly impact execution time.
Solution Approach 2:
The patent implements partial error checking where slave requests serve as redundancy for error detection but do not require full independent validation. The comparison logic performs selective checking focused on critical error modes, providing sufficient data integrity protection without the overhead of complete duplicate validation, thus minimizing time loss while maintaining reliability.
Data Source
AI summary
A system and method for protecting memory instructions against faults are described. The system and method include converting the slave instructions to dummy operations, modifying memory arbiter to issue up to N master and N slave global/shared memory instructions per cycle, sending master memory requests to memory system, using slave requests for error checking, entering master requests to the GM/LM FIFO, storing slave requests in a register, and comparing the entered master requests with the stored slave requests.