Non-blocking Memory Management Unit for GPU Page Fault Handling

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Solution Overview

Problem

Graphics processor units (GPUs) face stalls due to page faults, which are problematic because they cannot perform context switches like central processing units (CPUs), leading to visible user impacts and limitations in supporting virtual memory, often requiring all needed pages to be loaded before rendering to prevent faults.

Innovation Solution

Implementing a memory management unit (MMU) that handles page faults by sending responses indicating faults to pipeline stages, allowing them to replay requests once criteria are met, and continuing to service requests from other stages without blocking, enabling pages to be loaded as needed rather than requiring all pages to be loaded beforehand.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the MMU blocks to service a page fault, then the page fault can be handled correctly, but the pipeline stalls and rendering efficiency decreases

Engineering Contradiction:
Improvepage fault handling correctnessVSAvoidrendering efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent segments the page fault handling process into multiple independent stages: (1) The MMU identifies a page fault and sends a fault indication to the pipeline stage without blocking; (2) The pipeline stage marks the request for replay and continues processing other requests; (3) The operating system services the page fault in the background; (4) Once the fault is resolved, the pipeline stage replays the marked request. This segmentation allows the MMU to handle faults correctly while the pipeline continues processing, eliminating stalls and maintaining rendering efficiency.

Inventive Principle:
Principle #1Segmentation

2Reliability

If all needed pages are loaded before rendering, then page faults are prevented, but memory usage increases and flexibility decreases

Engineering Contradiction:
Improvepage fault preventionVSAvoidmemory usage
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent implements preliminary action by having the MMU proactively identify page faults before they cause pipeline stalls. When a page fault is detected, the MMU immediately sends a fault indication to the pipeline stage and marks the request for replay, allowing the operating system to service the fault in advance. This preliminary detection and marking mechanism ensures that when the fault is resolved, the pipeline can resume without interruption, preventing faults rather than reacting to them.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces dynamic page loading through the replay mechanism. Instead of statically loading all pages beforehand, the system dynamically loads pages on-demand: requests that cause page faults are marked and replayed after the operating system services them. This dynamic approach allows the system to load only the pages that are actually needed, adapting to the real-time memory requirements of the rendering pipeline while maintaining the illusion of continuous processing.

Inventive Principle:
Principle #15Dynamics

3Loss of time

If the GPU performs context switch, then other processes can run, but the GPU cannot switch contexts like CPU

Engineering Contradiction:
Improvepage fault service timeVSAvoidcontext switching capability
Core Design Contradiction:
Loss of timeVSAdaptability or versatility

Solution Approach 1:

The patent introduces an intermediary mechanism between the GPU pipeline and the operating system: the replayable request marker. When a page fault occurs, instead of blocking the pipeline or requiring context switching, the system uses this intermediary marker to communicate the fault condition to the pipeline stage. The marked request acts as a placeholder that allows the operating system to service the fault independently while the GPU continues rendering other frames. This intermediary mechanism enables asynchronous fault handling without context switching, allowing the GPU to maintain its rendering workflow while the operating system handles memory management in parallel.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS9652560B1Non-blocking memory management unit
Publication Date: 2017.05.16 APPLE INC
  • US9652560B1 patent drawing
  • US9652560B1 patent drawing
  • US9652560B1 patent drawing

AI summary

Techniques are disclosed relating to handling page faults created by a processor unit. In some embodiments, such techniques may be used within the context of graphics processor units (GPUs) to reduce the chances that a page fault will result in a GPU-pipeline stall. In one embodiment, a processor includes a graphics processor pipeline and a memory management unit. The graphics processor pipeline includes a plurality of pipeline stages. The memory management unit is configured to determine that a first data request from a first of the plurality of pipeline stages causes a page fault, and to service requests from one or more others of the plurality of pipeline stages while the page fault is being serviced.