Memory-Based Semaphores for GPU Engine Synchronization

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Solution Overview

Problem

Coordination between different processing engines in GPUs is resource-intensive due to the need for efficient synchronization of intermediate values and commands, leading to suboptimal resource allocation and increased power consumption.

Innovation Solution

Implementing memory-based semaphores for synchronization between engines, using commands like MI_SEMAPHORE_SIGNAL and MI_SEMAPHORE_WAIT to manage context switching and resource allocation, reducing memory access latency and improving hardware utilization by allowing smart sampling of semaphore data.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional coordination mechanisms are used between processing engines, then synchronization of intermediate values and commands is achieved, but resource consumption increases and power consumption rises

Engineering Contradiction:
Improvesynchronization reliabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent extracts the synchronization signaling function from traditional engine-to-engine communication and relocates it to memory-based operations. Producer engines write semaphore values to memory locations, and consumer engines poll these memory locations, eliminating the need for continuous inter-engine signaling protocols and reducing coordination overhead.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

Memory-based semaphores serve as an intermediary between producer and consumer engines. Instead of engines directly coordinating with each other, they interact through shared memory locations that contain semaphore values, decoupling the communication path and reducing direct coordination resource consumption.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If frequent context switching is performed for engine coordination, then synchronization is maintained, but hardware utilization decreases and performance is reduced

Engineering Contradiction:
Improvesynchronization accuracyVSAvoidhardware utilization
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

Producer engines perform preliminary actions by writing semaphore values to memory locations before consumer engines need the synchronized data. Consumer engines can then poll these pre-written values at their convenience, allowing asynchronous operation and reducing the need for immediate context switching and coordination interruptions.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If traditional semaphore implementation is used, then engine synchronization is achieved, but memory access latency increases

Engineering Contradiction:
Improvesynchronization correctnessVSAvoidmemory access latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent changes the implementation parameters of semaphores from traditional register-based or hardware-based mechanisms to memory-based storage. This parameter change allows for more flexible memory access patterns and enables smart sampling strategies where consumer engines can efficiently poll semaphore values without incurring excessive latency penalties.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10078879B2Process synchronization between engines using data in a memory location
Publication Date: 2018.09.18 INTEL CORP
  • US10078879B2 patent drawing
  • US10078879B2 patent drawing
  • US10078879B2 patent drawing

AI summary

Memory-based semaphores are described that are useful for synchronizing processes between different processing engines. In one example, operations include executing a first process at a first processing engine, the executing including updating a memory register, sending a signal from the first processing engine to a second processing engine that the memory register has been updated, the signal including a memory register address to identify the updated memory register inline data and a dataword, fetching data from the memory register by the second processing engine, comparing the fetched data to the received dataword, and conditionally executing a next command of a second process at the second processing engine based on the comparison.