Mid-command buffer preemption for GPU workload latency

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Solution Overview

Problem

In computing environments, there is a challenge in managing GPU workloads to balance time-sensitive and massive contexts, leading to perceptible latency when switching between them, which affects the user experience.

Innovation Solution

Implementing mid-command buffer preemption using a ring buffer mechanism that allows for asynchronous context switching, where the GPU can preempt ongoing workloads and switch to time-sensitive contexts quickly, reducing preemption latency by updating the head pointer and using arbitration commands to manage instruction sequences.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If the OS schedules contexts based on time slicing and priority, then massive contexts can be executed, but time-sensitive contexts experience perceptible latency when switching

Engineering Contradiction:
Improvecontext switching latencyVSAvoidGPU execution throughput
Core Design Contradiction:
Loss of timeVSProductivity

Solution Approach 1:

The batch buffer is segmented into multiple command sequences with arbitration commands inserted at specific points. This allows the GPU to execute commands in batches while providing interruption points for context preemption, reducing context switching latency without completely sacrificing throughput by allowing partial batch execution.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Arbitration commands are periodically inserted within batch buffers at strategically chosen points. This periodic structure allows the system to maintain regular GPU execution flow while creating scheduled opportunities for context preemption, balancing throughput maintenance with responsive context switching.

Inventive Principle:
Principle #19Periodic action

2Adaptability or versatility

If the GPU executes batch buffers continuously, then productivity is maintained, but the ability to preempt for time-sensitive contexts is limited

Engineering Contradiction:
Improvecontext preemption capabilityVSAvoidGPU execution efficiency
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

Arbitration commands are pre-inserted into batch buffers at optimal locations before submission to the GPU. This preliminary placement of preemption points ensures that when context preemption is needed, the GPU can efficiently execute to the next arbitration command and switch contexts without disrupting the overall execution flow, maintaining both adaptability and productivity.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Arbitration commands serve as intermediary instructions within the batch buffer that mediate between continuous GPU execution and context preemption requirements. These special commands allow the GPU to maintain its productive execution mode while providing controlled interruption points that enable adaptable context switching when time-sensitive contexts arise.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Loss of time

If context switching occurs at batch buffer boundaries, then execution simplicity is maintained, but preemption latency increases to multiple milliseconds

Engineering Contradiction:
Improvepreemption latencyVSAvoidcommand buffer management
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The batch buffer is divided into smaller command sequences separated by arbitration commands. This segmentation allows preemption to occur at finer-grained intervals within the batch buffer rather than only at boundaries, significantly reducing preemption latency while maintaining manageable complexity through structured division of commands.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system transitions from static batch buffer execution to dynamic execution with embedded arbitration points. This allows the GPU to adapt its execution flow dynamically, providing preemption capabilities at multiple locations within batch buffers based on timing requirements, reducing latency without requiring complete restructuring of the command buffer management system.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS9659342B2Mid command buffer preemption for graphics workloads
Publication Date: 2017.05.23 INTEL CORP
  • US9659342B2 patent drawing
  • US9659342B2 patent drawing
  • US9659342B2 patent drawing

AI summary

Mid-command buffer preemption is described for graphics workloads in a graphics processing environment. In one example, instructions of a first context are executed at a graphics processor, the first context has a sequence of instructions in an addressable buffer and at least one of the instructions is a preemption instruction. Upon executing the preemption instruction, execution of the first context is stopped before the sequence of instructions is completed. An address is stored for an instruction with which the first context will be resumed. The second context is executed, and upon completion of the execution of the second context, the execution of the first context is resumed at the stored address.