GPU Memory Reconfiguration with Mixed Pages and Cache Bank Shifts

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Solution Overview

Problem

Current graphics processing units (GPUs) face challenges in dynamically reconfiguring memory to optimize performance across various operations, such as graphics processing and machine learning tasks, due to limitations in cache management and memory allocation strategies.

Innovation Solution

The implementation of a dynamic reconfiguration method for cache memory bank assignments based on hardware statistics, enabling virtual memory address translation using mixed page sizes and creating heterogeneous processing systems with near and far regions in the cache hierarchy.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If fixed function computational units are used to process graphics data, then processing efficiency for specific operations is improved, but adaptability to different operations and workloads deteriorates

Engineering Contradiction:
Improveprocessing efficiencyVSAvoidadaptability to different operations
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The patent implements dynamic reconfiguration of cache memory bank assignments based on detected workload types. The system transitions from static cache allocation to dynamic allocation that adapts to different operational modes (graphics processing vs. machine learning tasks), allowing the same hardware to optimize performance across diverse workloads without requiring separate fixed-function units for each operation type.

Inventive Principle:
Principle #15Dynamics

2Productivity

If cache memory is dedicated to specific operations, then performance for those operations is improved, but memory utilization efficiency deteriorates when workloads change

Engineering Contradiction:
Improveperformance for specific operationsVSAvoidmemory utilization efficiency
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The system changes the parameters of cache memory allocation dynamically based on workload detection. When a workload type is detected (graphics or machine learning), the system reconfigures which cache memory banks are assigned to which processing units, thereby optimizing memory utilization efficiency while maintaining high performance for the current operation type.

Inventive Principle:
Principle #35Parameter changes

3Device complexity

If static memory allocation is used, then system complexity is reduced, but performance optimization across varying workloads deteriorates

Engineering Contradiction:
Improvesystem complexityVSAvoidperformance optimization
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent implements self-service through automatic workload detection and dynamic reconfiguration. The system automatically detects the type of workload being executed and reconfigures cache memory assignments without external intervention, maintaining low system complexity while achieving performance optimization across varying workloads through autonomous adaptation.

Inventive Principle:
Principle #25Self-service

Data Source

PatentEP3938914B1Dynamic memory reconfiguration
Publication Date: 2024.10.09 INTEL CORP
  • EP3938914B1 patent drawingFigure 1
  • EP3938914B1 patent drawingFigure 2A
  • EP3938914B1 patent drawingFigure 2B

AI summary

Embodiments described herein provide techniques to enable the dynamic reconfiguration of memory on a general-purpose graphics processing unit. One embodiment described herein enables dynamic reconfiguration of cache memory bank assignments based on hardware statistics. One embodiment enables for virtual memory address translation using mixed four kilobyte and sixty-four kilobyte pages within the same page table hierarchy and under the same page directory. One embodiment provides for a graphics processor and associated heterogenous processing system having near and far regions of the same level of a cache hierarchy.