GPU Multi-Level Data Structures for Faster Semiconductor Simulation

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Solution Overview

Problem

Existing semiconductor process simulation methods are inefficient and time-consuming due to the sequential operation of central processing units (CPUs), which hinder the parallelization of complex circuit design and testing processes, leading to increased costs and potential design flaws.

Innovation Solution

Implementing a multi-level data structure on a graphics processing unit (GPU) for semiconductor process simulation, utilizing a fine grid level for storing fine grid data and a coarse level for compressed data or pointers, enabling parallelized data processing and efficient memory management.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If CPU-based sequential processing is used for semiconductor process simulation, then the simulation can be performed with simple hardware architecture, but the simulation time becomes excessively long and productivity is low

Engineering Contradiction:
Improvesimulation speedVSAvoidsimulation time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The simulation domain is segmented into multiple blocks, each processed independently by different GPU threads. The fine grid is divided into chunks that can be processed in parallel, enabling simultaneous computation across multiple regions of the substrate, thereby dramatically reducing total simulation time while maintaining accuracy

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a hierarchical data structure with multiple levels (coarse grid and fine grid) to manage the simulation data. This multi-level approach enables efficient memory hierarchy utilization and parallel processing by organizing data across different spatial resolutions, transforming the sequential CPU approach into a parallel GPU-based system

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Measurement precision

If a fine grid is used to represent the substrate for high simulation accuracy, then the simulation precision is improved, but the memory requirement and data processing complexity increase significantly

Engineering Contradiction:
Improvesimulation accuracyVSAvoiddata structure complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The fine grid is segmented into multiple chunks that can be independently managed. Each chunk contains a subset of fine grid points and can be processed separately, reducing the memory footprint and allowing selective loading of data based on simulation needs, thereby maintaining accuracy while managing complexity

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements a nested data structure where coarse grid cells contain references to fine grid chunks. This multi-level hierarchy allows the system to store detailed fine grid information only where needed while using compressed coarse grid data elsewhere, reducing overall memory requirements and data structure complexity

Inventive Principle:
Principle #7Nested doll (Nesting)

3Reliability

If all fine grid data is stored in memory simultaneously, then the simulation can access complete data, but the memory consumption increases and memory management becomes inefficient

Engineering Contradiction:
Improvedata completenessVSAvoidmemory consumption
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The fine grid data is segmented into discrete chunks that can be selectively loaded into memory based on the current simulation requirements. This allows the system to maintain data completeness for active regions while reducing overall memory consumption by unloading or compressing data for regions not currently being processed

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The memory management system dynamically adjusts which fine grid chunks are loaded into memory based on the simulation progress and front position. The system transitions between different memory states (compressed/coarse vs. decompressed/fine) as needed, optimizing the balance between data completeness and memory consumption throughout the simulation

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS12361509B1Semiconductor process simulation on graphics processing unit (GPU) with multi-level data structure
Publication Date: 2025.07.15 SYNOPSYS INC
  • US12361509B1 patent drawing
  • US12361509B1 patent drawing
  • US12361509B1 patent drawing

AI summary

In an example, a multi-level data structure is defined including fine grid (FG) and coarse levels. The FG level is configured to store FG data of FG points. The coarse level is configured to store, for a respective chunk of FG points, compressed FG data and/or a pointer to corresponding FG data of the respective chunk. First chunks are identified by a graphics processing unit (GPU) and include each chunk of the FG points including one or more of: (i) that includes a FG point in a level set layer L0 (LSL0), and (ii) that neighbors a chunk that includes the FG point in the LSL0. Memory of the GPU is allocated for the first chunks that have respective compressed FG data to be decompressed. Level set values of the FG points in the LSL0 stored in the FG level in the allocated memory are updated by the GPU.