GPU Multiple Load Instruction for Memory Row Access
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Solution Overview
Problem
Current graphic processing units (GPUs) face inefficiencies in data loading times, which hinder performance due to the need for multiple memory transactions and lack of optimized instructions for loading data from multiple memory rows into registers.
Innovation Solution
A method and GPU architecture that utilize a multiple load instruction comprising first, second, and third instructions to load data from multiple memory rows into registers, where the second instruction writes control information including mask bits, span, and stride fields to efficiently select and sequence data, and the third instruction stores data sequentially based on this information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional sequential load instructions are used to load data from memory rows, then the GPU can load data one row at a time, but the time required to execute instructions increases and performance deteriorates
Solution Approach 1:
The patent combines multiple sequential load instructions into a single multiple load instruction that can load data from multiple memory rows simultaneously into different registers. This merging of operations reduces the total number of instructions executed and the time required for data loading, thereby improving GPU performance without increasing instruction execution time.
Solution Approach 2:
The patent introduces a new instruction type (multiple load instruction) that operates in a different dimension from traditional sequential loads. Instead of loading one row at a time in a linear sequence, the multiple load instruction enables parallel loading across multiple rows simultaneously, effectively adding a parallelism dimension to the data loading operation.
2Productivity
If multiple separate load instructions are used to load data from multiple memory rows, then data can be loaded from different rows, but the number of memory transactions increases and efficiency decreases
Solution Approach 1:
The patent merges multiple separate load instructions into a single multiple load instruction that handles data loading from multiple memory rows concurrently. This reduces the number of memory transactions from multiple sequential transactions to a single coordinated transaction, thereby improving memory access efficiency and reducing the complexity of memory operations.
Solution Approach 2:
The multiple load instruction performs preliminary coordination of multiple data loading operations, preparing the memory address pointers and register destinations in advance. This preliminary action enables the subsequent data loading to occur in a more efficient, consolidated manner rather than through multiple separate transactions.
3Adaptability or versatility
If conventional load instructions load data to a single register, then the instruction format is simple, but the capability to load data from multiple rows simultaneously is limited
Solution Approach 1:
The multiple load instruction is designed with multi-functionality to handle data loading from multiple memory rows simultaneously while maintaining compatibility with existing GPU architectures. The instruction incorporates control information fields (row pointer, register pointer, increment values) that enable versatile operation across different data loading scenarios without requiring completely new instruction sets.
Solution Approach 2:
The instruction format of the multiple load instruction embeds multiple control parameters within a unified structure. The control information includes nested fields for row pointers, register pointers, and increment values, allowing the single instruction to encapsulate and coordinate multiple data loading operations without proportionally increasing the overall instruction complexity.
Data Source
AI summary
A method of operating a graphic processor unit includes detecting from a program code a code area that instructs a load/store unit to load data stored in a plurality of rows of a memory to registers of a register file using a scheduler; and, using a load/store unit, loading data to the at least one register in response to instructions corresponding to the code area. A second instruction of the instructions instructs the load/store unit to write control information in a control register of the at least one register. The control information includes at least mask bits designating selected rows of the memory that store data to be loaded from the plurality of rows of the memory, a span field representing a relationship of the plurality of rows of the memory to each other and a stride field. A third instruction of the instruction instructs the load/store unit to store the data sequentially from a row of the memory corresponding to an address written in a base register of the register file to a first register of the register file, according to the control information.