GPU Packet Processing via RDMA and Shared Memory

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Solution Overview

Problem

Current parallel processing systems face inefficiencies in data communication between compute nodes and GPUs, particularly due to signal transmission delays and memory consistency issues, which hinder effective packet processing and data transfer.

Innovation Solution

The system employs a GPU-based architecture with a PCIe bus connection between the GPU and CPU, utilizing a GPU memory pool exposed to the NIC, and an RDMA module to facilitate direct data transfer between the GPU memory and NIC, bypassing CPU intervention and optimizing signal travel times.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If data transfer goes through CPU memory, then memory consistency is maintained, but signal transmission delay increases

Engineering Contradiction:
Improvedata transfer speedVSAvoidsignal transmission delay
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The patent introduces an RDMA module as an intermediary component between the GPU and NIC, enabling direct memory access without CPU intervention. The RDMA module handles data transfer operations independently, allowing the GPU to write data directly to NIC memory through a dedicated memory pool, thus eliminating CPU bottlenecks and reducing signal transmission delay while maintaining data consistency through controlled access paths.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent segments the memory system into distinct memory pools: GPU memory, NIC memory, and a shared memory pool accessible by both GPU and NIC. This segmentation allows parallel operations where the GPU can write to the shared pool while the NIC independently reads from it, eliminating the need for sequential CPU-mediated transfers and reducing overall transmission delay.

Inventive Principle:
Principle #1Segmentation

2Productivity

If CPU intervenes in data transfer, then memory consistency is ensured, but processing efficiency decreases

Engineering Contradiction:
Improvepacket processing efficiencyVSAvoidCPU intervention time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent implements self-service mechanisms where the GPU and NIC autonomously manage data transfer operations. The GPU independently writes processed packets to the shared memory pool, and the NIC independently retrieves and transmits data, both operations occurring without CPU intervention. This self-service approach eliminates CPU bottlenecks and significantly improves packet processing efficiency.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The RDMA module serves as an intermediary that enables direct communication between GPU and NIC, bypassing the CPU entirely for data transfer operations. This intermediary mechanism allows both devices to operate independently and simultaneously, improving productivity by eliminating CPU intervention time while maintaining system coordination through the standardized memory interface.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Speed

If direct GPU-NIC memory access is implemented, then signal transmission delay is reduced, but memory consistency issues arise

Engineering Contradiction:
Improvedata transfer speedVSAvoidmemory consistency
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent applies local quality by creating a dedicated shared memory pool with specific access characteristics tailored for GPU-NIC communication. This memory region has controlled access permissions where both GPU and NIC can read and write, but with defined ownership and access protocols. The local quality of this memory region ensures reliable data exchange while maintaining high transfer speeds, as each device operates with optimized access patterns for its specific needs.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11861758B2Packet processing acceleration using parallel processing
Publication Date: 2024.01.02 NVIDIA CORP
  • US11861758B2 patent drawing
  • US11861758B2 patent drawing
  • US11861758B2 patent drawing

AI summary

Apparatuses, systems, and techniques to process packet data in parallel. In at least one embodiment, packet data is processed by (e.g., one or more algorithms expressed in CUDA code executing on) a Graphics Processing Unit (“GPU”).