GPU-Initiated Packet Scheduling for 5G Transmission Bottlenecks

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing data transmission methods in 5G networks are computationally intensive due to the limited processing capabilities of network interface cards and CPUs, leading to bottlenecks and compromised communication efficacy.

Innovation Solution

Shift packet preparation, scheduling, and transmission responsibilities from CPUs to GPUs, utilizing their parallel processing capabilities to prepare and transmit data packets with precise timing instructions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If packet preparation and scheduling is performed by CPU, then transmission timing control is achieved, but CPU processing bottleneck degrades system performance

Engineering Contradiction:
Improvetransmission timing controlVSAvoidsystem performance
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent extracts the packet preparation and scheduling functions from the CPU and relocates them to the GPU. The GPU receives packet data from memory, prepares packet descriptors with timing information, and schedules transmissions independently, thereby relieving the CPU of these computationally intensive tasks while maintaining precise transmission timing control through the GPU's parallel processing capabilities.

Inventive Principle:
Principle #2Taking out (Extraction)

2Productivity

If packet preparation is performed by CPU, then data transmission is achieved, but limited processing capabilities create bottlenecks

Engineering Contradiction:
Improvepacket transmission rateVSAvoidprocessing capability requirements
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent substitutes the CPU's sequential processing mechanism with the GPU's parallel processing mechanism for packet preparation tasks. The GPU leverages its numerous cores to simultaneously prepare multiple packet descriptors, significantly increasing packet transmission rates and overcoming the processing bottlenecks inherent in CPU-based approaches.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Ease of operation

If CPU prepares packet descriptors, then transmission scheduling is controlled, but additional workloads degrade overall system performance

Engineering Contradiction:
Improvetransmission scheduling controlVSAvoidoverall system performance
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The patent implements self-service by enabling the GPU to autonomously prepare packet descriptors and manage transmission scheduling without requiring continuous CPU intervention. The GPU independently accesses packet data from memory, generates descriptors with timing information, and controls transmission scheduling, thereby maintaining ease of operation while eliminating the performance degradation caused by CPU workload.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS12418906B2System and method for GPU-initiated communication
Publication Date: 2025.09.16 NVIDIA CORP
  • US12418906B2 patent drawing
  • US12418906B2 patent drawing
  • US12418906B2 patent drawing

AI summary

A computer based system and method for sending data packets over a data network may include: preparing data packets and packet descriptors on one or more graphical processing units (GPUs); associating packets with a packet descriptor, which may determine a desired transmission time of the packets associated with that descriptor; receiving an indication of a clock time; and physically transmitting packets via an output interface, at a clock time corresponding to the desired transmission time. A computer based system and method for GPU-initiated communication over a 5G data network may include allocating one or more memory buffers in GPU memory; performing at least one 5G signal processing procedure by a GPU; preparing descriptors for a plurality of packets, where each packet includes allocated memory buffers, and where the descriptors provide scheduling instructions for the packets; and triggering the sending of packets over the network based on prepared descriptors.