GPU Parallel CRC Computation for Low-Latency Data Transmission

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Solution Overview

Problem

Current methods for computing cyclic redundancy checks (CRCs) in communication systems are slow due to serial processing, which is inefficient for high-speed data transmission in applications like 5G networks, where quick error detection and correction are crucial.

Innovation Solution

Implementing parallel computing architectures, specifically using graphics processing units (GPUs) to process CRCs in parallel, by breaking input data into segments and using precomputed generator segments to reduce the computational effort through modular polynomial multiplications and additions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If serial processing is used for CRC computation, then device complexity is reduced, but processing speed decreases

Engineering Contradiction:
ImproveCRC processing speedVSAvoidcomputational complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent divides the input data into multiple segments and processes each segment in parallel using separate computational units. Each segment is processed through its own polynomial multiplication and addition operations simultaneously, rather than sequentially. This segmentation enables the system to achieve higher processing speeds by utilizing multiple processing paths concurrently.

Inventive Principle:
Principle #1Segmentation

2Loss of time

If parallel computing architectures are implemented, then CRC processing speed increases, but latency is reduced

Engineering Contradiction:
Improveprocessing latencyVSAvoidarchitecture complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent precomputes generator segments and stores them in lookup tables before actual CRC processing begins. These precomputed values are prepared in advance and made readily available for parallel processing operations. By performing this computation beforehand, the system eliminates the need for real-time polynomial generation during parallel processing, thereby reducing overall latency while maintaining architectural complexity at acceptable levels.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If precomputed generator segments are used, then computational effort is reduced, but memory requirements increase

Engineering Contradiction:
Improveprocessing efficiencyVSAvoidmemory storage
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent stores precomputed generator segments in localized lookup tables that are specifically optimized for the parallel processing units. Each processing unit has access to locally stored generator segments relevant to its specific computational tasks. This localized storage approach minimizes the memory footprint by only storing necessary precomputed values close to where they are needed, rather than maintaining large centralized storage, thereby improving processing efficiency while controlling memory requirements.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12003253B2Performing cyclic redundancy checks using parallel computing architectures
Publication Date: 2024.06.04 NVIDIA CORP
  • US12003253B2 patent drawing
  • US12003253B2 patent drawing
  • US12003253B2 patent drawing

AI summary

Apparatuses, systems, and techniques to compute cyclic redundancy checks use a graphics processing unit (GPU) to compute cyclic redundancy checks. For example, in at least one embodiment, an input data sequence is distributed among GPU threads for parallel calculation of an overall CRC value for the input data sequence according to various novel techniques described herein.