Partial Sorting for Coherency Recovery in GPU Compute Units
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional computer architectures face inefficiencies in processing non-coherent data on parallel processing units, leading to increased processing cycles and power consumption due to the need for software-based partial sorting methods, which are not efficient in recovering execution coherency.
Innovation Solution
The implementation of partial sorting using existing hardware along the memory path, such as local data share (LDS) memory, L0 cache memory, and register files, employing counting sort with lossy binning and bit-pack instructions to efficiently recover coherency in divergent workloads, without the overhead of software execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software-based partial sorting methods are used to recover execution coherency, then coherency recovery is achieved, but processing cycles and power consumption increase
Solution Approach 1:
The patent replaces software-based sorting mechanisms with hardware-based sorting circuits integrated into the parallel processing unit. The sorting logic is implemented as dedicated hardware circuits that operate in parallel with the processing elements, eliminating the need for software intervention and reducing processing cycles while maintaining coherency recovery capability
Solution Approach 2:
The patent introduces a hardware sorting network as an intermediary component between the memory system and the processing elements. This sorting network pre-arranges data in coherent order before data reaches the processing elements, allowing the main processing pipeline to operate efficiently without software-based sorting overhead
2Reliability
If software-based partial sorting methods are used to recover execution coherency, then coherency recovery is achieved, but power consumption increases
Solution Approach 1:
The patent replaces power-intensive software sorting operations with energy-efficient hardware sorting circuits. The hardware circuits perform sorting operations using dedicated logic gates and comparators that consume significantly less power than general-purpose processor execution of sorting algorithms, thereby reducing overall power consumption while maintaining coherency recovery
Solution Approach 2:
The patent implements preliminary sorting of data in hardware before data enters the main processing pipeline. By pre-arranging data in coherent order using hardware circuits, the system avoids the need for repeated software-based sorting operations during processing, thereby reducing cumulative power consumption
3Productivity
If existing hardware along the memory path is used for partial sorting, then processing efficiency is improved, but memory overhead increases
Solution Approach 1:
The patent designs the hardware sorting circuits to utilize existing memory infrastructure along the data path for temporary storage during sorting operations. The same memory resources are shared between sorting operations and normal data processing, eliminating the need for dedicated sorting memory and minimizing additional memory overhead while maintaining high processing efficiency
Data Source
AI summary
Devices and methods for partial sorting for coherence recovery are provided. The partial sorting is efficiently executed by utilizing existing hardware along the memory path (e.g., memory local to the compute unit). The devices include an accelerated processing device which comprises memory and a processor. The processor is, for example, a compute unit of a GPU which comprises a plurality of SIMD units and is configured to determine, for data entries each comprising a plurality of bits, a number of occurrences of different types of the data entries by storing the number of occurrences in one or more portions of the memory local to the processor, sort the data entries based on the determined number of occurrences stored in the one or more portions of the memory local to the processor and execute the sorted data entries.