Concurrent GPU-PIM Memory Execution With MPU Request Orchestration

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Solution Overview

Problem

Existing memory management systems in high-performance computing and AI systems lack efficient concurrent execution of processing-in-memory operations, leading to reduced compute performance and increased latency due to serialized execution and mode changes between GPU and DRAM die processing.

Innovation Solution

A hybrid architecture with concurrent GPU-PIM execution is implemented, allowing simultaneous access to high-bandwidth memory by both GPU and in-memory processing units, facilitated by a memory processing unit agent that orchestrates data movement and processing across multiple memory dies.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If serialized execution between GPU and DRAM die processing is used, then device complexity is reduced, but productivity decreases due to increased latency and reduced compute performance

Engineering Contradiction:
Improvecompute performanceVSAvoidexecution management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

A memory processing unit (MPU) agent is introduced as an intermediary component that manages and orchestrates concurrent execution between GPU and PIM operations. The MPU agent receives memory requests, determines whether to execute them on the DRAM die or forward them to the GPU, and coordinates data movement between memory banks and processing units, thereby enabling concurrent execution without requiring complex external management systems

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The system merges GPU processing capabilities with PIM processing capabilities into a unified memory system. The DRAM die contains both memory banks and processing units that can execute operations concurrently with the GPU, creating a hybrid architecture where memory and processing are integrated at the same die level, allowing simultaneous access without serialized execution

Inventive Principle:
Principle #5Merging (Combining)

2Adaptability or versatility

If mode changes between GPU and DRAM die processing are implemented, then adaptability improves, but loss of time increases due to switching overhead and latency

Engineering Contradiction:
Improveprocessing flexibilityVSAvoidexecution latency
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The MPU agent performs preliminary determination of the execution mode (DRAM die or GPU) before actual processing begins. By pre-evaluating memory requests and deciding the execution path in advance, the system avoids runtime mode switching and reduces latency associated with dynamic changes between processing modes

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The memory system is segmented into distinct functional regions: memory banks for data storage and processing units for computation, all located on the same DRAM die. This segmentation allows independent concurrent operation of memory access and processing tasks, eliminating the need for time-consuming mode changes between GPU and DRAM processing

Inventive Principle:
Principle #1Segmentation

3Productivity

If concurrent GPU-PIM execution is enabled, then throughput increases, but device complexity increases due to coordinated data movement across multiple memory dies

Engineering Contradiction:
ImprovethroughputVSAvoiddata movement coordination
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The MPU agent serves as a mediator that simplifies the coordination of concurrent data movements between GPU and PIM operations. It manages data transfer between memory banks and processing units, handles request routing, and ensures proper synchronization without requiring complex external control systems

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

Processing units are nested within the DRAM die structure, with memory banks and processing units organized in a hierarchical manner on the same die. This nesting allows direct, low-latency data movement between storage and processing elements, reducing the complexity of coordinating data transfer across multiple dies while enabling concurrent GPU-PIM execution

Inventive Principle:
Principle #7Nested doll (Nesting)

Data Source

PatentUS20260003628A1Systems and methods of concurrent execution in processing in memory systems
Publication Date: 2026.01.01 SAMSUNG ELECTRONICS CO LTD
  • US20260003628A1 patent drawing
  • US20260003628A1 patent drawing
  • US20260003628A1 patent drawing

AI summary

Provided are systems, methods, and apparatuses for systems and methods of concurrent execution of processing-in-memory (PIM) operations. In one or more examples, the systems, devices, and methods include receiving a memory request for processing on a memory die; modifying the memory request based on the memory request being configured for processing on the memory die; and sending the modified memory request to a processing unit on the memory die. In one or more examples, the systems, devices, and methods include enabling the memory die for processing of PIM on-die processing and disabling the memory die for off-die processing.