GPU Power-Well Telemetry for Dynamic State Management

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Solution Overview

Problem

Current power management techniques for graphics processing units (GPUs) face challenges in balancing performance and power efficiency, particularly in handling mixed workloads that combine burstiness and idleness, leading to suboptimal power-gating decisions and performance losses.

Innovation Solution

Implementing advanced power state management by measuring detailed telemetry on idle/active transitions of each power-well and using performance and energy equations to dynamically determine the optimal idle hysteresis and power-gating strategies, allowing for reduced operating frequency during idle periods to enhance energy savings with minimal performance loss.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If power-gating is applied to save power during idle periods, then power consumption is reduced, but performance loss occurs when work needs to be executed

Engineering Contradiction:
Improvepower consumptionVSAvoidperformance
Core Design Contradiction:
Loss of energyVSProductivity

Solution Approach 1:

The patent implements dynamic power state management where the GPU transitions between different power states (fully on, partially powered down, fully off) based on real-time workload characteristics. The system dynamically adjusts the power-gating strategy by monitoring workload patterns and transitioning power wells between operational and powered-down states, optimizing the balance between power savings and performance readiness.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes power state parameters (voltage, clock frequency, power well states) based on workload analysis. By measuring detailed telemetry data and analyzing workload characteristics, the system adjusts power delivery parameters to match actual demand, reducing power consumption during idle periods while maintaining quick recovery capability when work arrives.

Inventive Principle:
Principle #35Parameter changes

2Loss of energy

If advanced power state management with detailed telemetry measurement is implemented, then power efficiency is improved, but device complexity increases

Engineering Contradiction:
Improvepower efficiencyVSAvoidsystem complexity
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The GPU system performs self-monitoring and self-management of power states through integrated telemetry measurement capabilities. The system automatically measures its own power well states, workload characteristics, and performance metrics, then autonomously makes power management decisions without requiring external control, reducing the need for additional complex control infrastructure.

Inventive Principle:
Principle #25Self-service

3Productivity

If power wells are kept on to avoid performance loss, then performance is maintained, but power consumption increases

Engineering Contradiction:
Improveperformance readinessVSAvoididle power consumption
Core Design Contradiction:
ProductivityVSUse of energy by stationary object

Solution Approach 1:

The patent divides the GPU power architecture into multiple independent power wells, each capable of being powered down separately. By segmenting the power delivery into discrete controllable units (power wells), the system can selectively power down specific functional blocks during idle periods while keeping other blocks operational, enabling granular power management that reduces overall power consumption without completely shutting down the GPU.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11533683B2Advanced graphics power state management
Publication Date: 2022.12.20 INTEL CORP
  • US11533683B2 patent drawing
  • US11533683B2 patent drawing
  • US11533683B2 patent drawing

AI summary

Methods and apparatus relating to advanced graphics Power State management are described. In one embodiment, measurement logic detects information about idle transitions and active transitions of a power-well of a processor. In turn, determination logic determines performance loss and/or energy gain based at least in part on the detected information and power-on latency of the power-well of the processor. Other embodiments are also disclosed and claimed.