GPU Work Distribution via Priority Slot Tracking

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Solution Overview

Problem

In graphics processing units (GPUs) with multiple replicated processing elements, efficiently distributing and tracking work to prevent high-priority tasks from being blocked by lower-priority tasks is challenging, especially as the number of shader cores increases, leading to performance and power consumption issues.

Innovation Solution

The implementation of primary control circuitry that maps logical slots to distributed hardware slots using various distribution modes, prioritization techniques, and affinity-based scheduling to ensure high-priority work is not blocked, including software overrides for dynamic remapping and reserved slots for critical tasks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If work is distributed to multiple replicated shader cores, then processing power and throughput are improved, but high-priority work may be blocked by lower-priority work

Engineering Contradiction:
Improveprocessing throughputVSAvoidquality of service guarantee
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent segments the distributed architecture into multiple independent replicated processing elements (shader cores), each capable of handling work independently. This segmentation allows high-priority work to be assigned to specific cores that are not blocked by lower-priority work on other cores, thereby maintaining quality of service guarantees while preserving high throughput.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces data master circuitry as an intermediary between the work queue and replicated shader cores. This intermediary tracks usage of distributed GPU resources and manages work distribution, enabling it to prevent blocking of high-priority work by lower-priority work through intelligent scheduling and resource allocation decisions.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If the number of shader cores is increased, then compute capability is improved, but work distribution and scheduling complexity increases

Engineering Contradiction:
Improvecompute capabilityVSAvoidwork distribution complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements replicated processing elements that are universal in nature - each shader core can execute any type of work (vertex shader, fragment shader, compute tasks). This universality simplifies work distribution because the same scheduling mechanisms can be applied regardless of the number of cores, and each core serves multiple potential functions.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

Each replicated processing element maintains its own state and can independently execute assigned work without requiring complex coordination with other cores. This self-service capability reduces scheduling complexity by eliminating the need for intricate inter-core communication and coordination mechanisms.

Inventive Principle:
Principle #25Self-service

3Productivity

If work is distributed across multiple processing elements, then processing capacity is improved, but tracking resource usage and preventing blocking becomes more difficult

Engineering Contradiction:
Improveprocessing capacityVSAvoidresource usage tracking
Core Design Contradiction:
ProductivityVSDifficulty of detecting and measuring

Solution Approach 1:

The patent implements feedback mechanisms where data master circuitry continuously monitors the state and resource usage of replicated processing elements. This feedback enables the system to track which cores are currently executing high-priority versus lower-priority work, allowing dynamic adjustments to prevent blocking and optimize resource allocation based on real-time conditions.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS12039368B2Priority inversion mitigation techniques
Publication Date: 2024.07.16 APPLE INC
  • US12039368B2 patent drawing
  • US12039368B2 patent drawing
  • US12039368B2 patent drawing

AI summary

Disclosed techniques relate to distributing graphics work based on priority. In some embodiments, circuitry implements a plurality of tracking slots for sets of graphics work. A set of graphics processor sub-units may each implement multiple distributed hardware slots. Control circuitry may attempt to assign a first set of graphics work having a first priority to a graphics processor sub-unit that is currently executing graphics work having an equal or higher priority than the first priority, where the first set of graphics work is from a first tracking slot. The control circuitry may, in response to a failure of the attempt, generate a signal to graphics software that indicates the failure, wherein the signal indicates the first tracking slot. Disclosed techniques may reduce or avoid problems relating to higher priority work being scheduled behind lower priority work.