GPU Private Memory Allocation With Dynamic Page Mapping
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Solution Overview
Problem
Existing graphics processing unit (GPU) memory management techniques face inefficiencies due to fixed private memory allocations, which do not adapt to varying memory needs and hinder memory space sharing between shader processors and other circuitry.
Innovation Solution
Implementing a memory allocator circuit that dynamically allocates and maps private memory spaces, allowing consolidation into a shared global memory space, with operations like reserve, translate-map, translate-no-map, and unmap to manage memory allocation efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If fixed private memory allocations are used in GPU, then memory management is simple, but memory efficiency is poor and memory space cannot be shared between shader processors and other circuitry
Solution Approach 1:
The patent implements dynamic memory allocation where the memory allocator circuit dynamically allocates and deallocates private memory spaces to shader processors based on runtime needs. The system transitions from fixed static allocation to dynamic allocation, allowing memory sizes and assignments to change during operation, thereby improving adaptability while managing complexity through automated allocation algorithms
Solution Approach 2:
The patent creates a unified global memory space that serves multiple functions: it acts as shared memory for shader processors, provides private memory spaces when needed, and enables memory sharing between different circuitry components. The memory allocator circuit manages this multi-functional memory system, allowing the same physical memory resources to serve multiple purposes and multiple consumers simultaneously
2Quantity of substance
If fixed private memory allocations are used, then memory management overhead is low, but overall memory usage is inefficient and software footprints are larger
Solution Approach 1:
The patent changes the allocation parameters from fixed predetermined values to dynamic values determined at runtime. The memory allocator circuit adjusts memory allocation parameters (size, address mapping, duration) based on actual usage patterns, allowing the system to optimize memory consumption while maintaining ease of operation through automated parameter management
Solution Approach 2:
The memory allocator circuit implements self-service mechanisms where memory is automatically allocated, mapped, and deallocated based on program execution needs without requiring manual intervention. The system monitors memory usage and automatically adjusts allocations, reducing the burden on software developers while improving memory efficiency
3Adaptability or versatility
If dynamic memory allocation is implemented, then memory flexibility and sharing capability improve, but memory management complexity increases
Solution Approach 1:
The patent introduces a memory allocator circuit as an intermediary component between the physical memory resources and the shader processors. This intermediary handles the complexity of dynamic allocation, address translation, and memory sharing coordination, shielding the shader processors from complexity while enabling advanced memory management features and sharing capabilities
Data Source
AI summary
Techniques are disclosed relating to dynamically allocating and mapping private memory for requesting circuitry. Disclosed circuitry may receive a private address and translate the private address to a virtual address (which an MMU may then translate to physical address to actually access a storage element). In some embodiments, private memory allocation circuitry is configured to generate page table information and map private memory pages for requests if the page table information is not already setup. In various embodiments, this may advantageously allow dynamic private memory allocation, e.g., to efficiently allocate memory for graphics shaders with different types of workloads. Disclosed caching techniques for page table information may improve performance relative to traditional techniques. Further, disclosed embodiments may facilitate memory consolidation across a device such as a graphics processor.