Direct GPU Interconnect via Private PCIe Bypassing North Bridge
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Solution Overview
Problem
Current systems supporting multiple graphics processing units (GPUs) face inefficiencies due to inter-GPU communication bottlenecks, such as high latency and bandwidth consumption, particularly when using PCIe links and north bridge chip routing, which hinder optimal graphics processing performance in applications like 3-D games and high-definition video.
Innovation Solution
A system and method that directly couples multiple GPUs via a private PCIe interface, bypassing the north bridge chip and system memory, allowing them to communicate through dedicated 8-lane PCIe links, thereby reducing latency and optimizing bandwidth usage between GPUs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple GPUs communicate through north bridge chip and system memory, then system compatibility is maintained, but communication latency increases and bandwidth is consumed
Solution Approach 1:
The patent segments the communication path by introducing a dedicated inter-GPU link that separates inter-GPU traffic from the traditional north bridge routing path. This allows multiple GPUs to communicate directly without sharing the north bridge bandwidth, thereby reducing latency while maintaining system compatibility through the existing PCIe interface standard.
Solution Approach 2:
The patent introduces a dedicated inter-GPU link as an intermediary communication channel between GPUs. This intermediary path bypasses the north bridge chip and system memory, providing a direct high-speed communication route that reduces latency without requiring changes to the overall system architecture or north bridge design.
2Device complexity
If multiple GPUs communicate through north bridge chip and system memory, then system simplicity is maintained, but bandwidth utilization becomes inefficient
Solution Approach 1:
The patent segments the bandwidth resources by dedicating a portion of the PCIe link bandwidth specifically for inter-GPU communication. This segmentation allows efficient bandwidth utilization for GPU-to-GPU data transfer while the remaining bandwidth continues to serve traditional PCIe functions, maintaining system simplicity without requiring complex routing infrastructure.
Solution Approach 2:
The patent adds a new dimension to the communication architecture by introducing a dedicated inter-GPU link layer. This new dimensional path operates parallel to the traditional north bridge routing, providing additional bandwidth capacity for inter-GPU communication without increasing the complexity of the existing PCIe interface or requiring modifications to the north bridge chip.
3Power
If PCIe links are used for GPU communication, then high bandwidth is achieved, but latency remains high due to routing through north bridge
Solution Approach 1:
The patent extracts the inter-GPU communication path from the traditional north bridge routing sequence. By taking out the north bridge and system memory from the communication path, the patent enables direct GPU-to-GPU data transfer that maintains high bandwidth capabilities while dramatically reducing the latency associated with sequential routing through multiple components.
Solution Approach 2:
The patent implements a direct inter-GPU link that allows data to rush through the communication path without stopping at the north bridge or system memory. This skipping of intermediate components eliminates the processing delays and routing overhead that would otherwise increase latency, while preserving the high bandwidth capacity of the PCIe interface.
Data Source
AI summary
Supporting multiple graphics processing units (GPUs) comprises a first path coupled to a north bridge device (or a root complex device) and a first GPU, which may include a portion of the first GPU's total communication lanes. A second communication path may be coupled to the north bridge device and a second GPU and may include a portion of the second GPU's total communication lanes. A third communication path may be coupled between the first and second GPUs directly or through one or more switches that can be configured for single or multiple GPU operations. The third communication path may include some or all of the remaining communication lanes for the first and second GPUs. As a nonlimiting example, the first and second GPUs may each utilize an 8-lane PCI express communication path with the north bridge device and an 8-lane PCI express communication path with each other.