GPU Processing Element Remapping for Yield

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Solution Overview

Problem

The manufacturing of high-performance graphics processing units is hindered by low yields due to the inclusion of numerous computational components in a single integrated circuit, leading to resource-intensive and costly manufacturing processes.

Innovation Solution

A method and system for remapping processing elements in a graphics processing unit, allowing for the disabling of defective elements and efficient use of functional ones by virtually addressing enabled processing elements and mapping them to physical addresses, thereby increasing yield and flexibility in testing and usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If numerous computational components are included in a single integrated circuit to achieve high-performance graphics processing, then processing power and functionality are improved, but manufacturing yield deteriorates due to increased complexity and higher probability of defects

Engineering Contradiction:
Improveprocessing powerVSAvoidmanufacturing yield
Core Design Contradiction:
PowerVSReliability

Solution Approach 1:

The graphics processing unit is divided into multiple independent processing elements (PEs) organized in a pipeline architecture. Each PE can be independently tested, enabled, or disabled through remapping, allowing defective elements to be isolated while maintaining functionality of good elements. This segmentation enables high processing power through parallel operation of multiple PEs while improving manufacturing yield by excluding only the defective portions.

Inventive Principle:
Principle #1Segmentation

2Productivity

If a deep pipeline architecture is used to maximize rendering throughput, then processing speed is improved, but the complexity of testing and configuring individual processing elements deteriorates

Engineering Contradiction:
Improverendering throughputVSAvoidtesting and configuration complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

A remapping mechanism is introduced as an intermediary layer between the pipeline stages and the physical processing elements. This remapping system abstracts the complexity of testing and configuration by providing a unified interface that automatically routes data to functional PEs while masking the presence of defective elements. The intermediary handles the complexity of managing multiple PEs in the deep pipeline, simplifying testing and configuration procedures.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Adaptability or versatility

If multiple processing elements are integrated to accelerate rendering operations, then functionality and performance are improved, but manufacturing cost and resource intensity deteriorate

Engineering Contradiction:
Improverendering functionalityVSAvoidmanufacturing cost
Core Design Contradiction:
Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The system dynamically changes the operational parameters of processing elements through enabling and disabling specific PEs based on their functional status. By remapping active processing elements to functional units, the system optimizes performance without requiring additional hardware. This parameter adjustment approach maintains high rendering functionality while reducing manufacturing costs by utilizing existing functional PEs rather than requiring perfect yield from all integrated elements.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS8711156B1Method and system for remapping processing elements in a pipeline of a graphics processing unit
Publication Date: 2014.04.29 NVIDIA CORP
  • US8711156B1 patent drawing
  • US8711156B1 patent drawing
  • US8711156B1 patent drawing

AI summary

A method and system for remapping units that are disabled to active units in a 3-D graphics pipeline. Specifically, in one embodiment, a method remaps processing elements in a pipeline of a graphics pipeline unit. Graphical input data are received. Then the number of enabled processing elements are determined from a plurality of processing elements. Each of the enabled processing elements are virtually addressed above a translator to virtually process the graphical input data. Then, the virtual addresses of each of the enabled processing elements are mapped to physical addresses of the enabled processing elements at the translator. The graphical input data are physically processed at the physical addresses of the enabled processing elements. In addition, each of the enabled processing elements are physically addressed below the translator to further process the graphical input data.