Compiler Register Allocation for GPU Non-Scalar Values
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Solution Overview
Problem
Compilers face challenges in efficiently allocating registers for non-scalar values in graphics processing unit (GPU) programs, as these values often require multiple registers and existing methods may lead to inefficient memory access and redundancy.
Innovation Solution
The compiler divides instructions for non-scalar values into operations on scalar values, allocating multiple physical registers to store these scalar values while maintaining their relationship, allowing for efficient register allocation and reduced redundancy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the compiler stores non-scalar values in multiple physical registers, then the access efficiency is improved, but the register allocation complexity increases
Solution Approach 1:
The compiler segments non-scalar values into their constituent scalar values, allowing each scalar to be stored in a separate physical register. This segmentation enables efficient register allocation by treating each scalar independently while maintaining their relationship through association metadata, thus improving access speed without overwhelming complexity.
Solution Approach 2:
The patent introduces a new dimension of register association by maintaining relationships between registers that store scalar constituents of non-scalar values. This associative dimension allows the compiler to track and manage multiple registers representing a single logical non-scalar value, resolving the complexity through structured relationship management.
2Productivity
If the compiler divides instructions for non-scalar values into scalar operations, then the register utilization is improved, but the instruction count increases
Solution Approach 1:
By segmenting non-scalar value operations into scalar operations, the compiler can allocate each scalar to an appropriate register, improving overall register utilization. Although this creates more instructions, the efficient register usage compensates by reducing memory access overhead and improving execution throughput.
Solution Approach 2:
The patent changes the parameter of value representation from non-scalar to scalar, enabling finer-grained register allocation. This parameter change allows the compiler to optimize register usage by assigning scalars to registers based on their specific characteristics and usage patterns, improving productivity despite increased instruction count.
3Productivity
If the compiler allocates multiple registers for non-scalar values, then the processing efficiency is improved, but the redundancy in the compiled program increases
Solution Approach 1:
The patent adds an associative dimension to track relationships between registers storing scalar constituents of non-scalar values. This allows the compiled program to maintain processing efficiency through proper register allocation while reducing redundancy by systematically managing which registers represent parts of the same logical value, enabling optimization opportunities in the compilation process.
Data Source
AI summary
In general, aspects of this disclosure describe a compiler for allocation of physical registers for storing constituent scalar values of a non-scalar value. In some example, the compiler, executing on a processor, may receive an instruction for operation on a non-scalar value. The compiler may divide the instruction into a plurality of instructions for operation on constituent scalar values of the non-scalar value. The compiler may allocate a plurality of physical registers to store the constituent scalar values.