GPU Register Promotion for Arrays of Structures in Divergent Control Flow

The patent segments the thread block execution into multiple warp groups, allowing different segments (warp groups) to execute different control flow paths simultaneously. Instead of all threads executing in lock-step, the thread block is divided into segments that can diverge and execute independently, resolving the contradiction between reduced overhead and maintained utilization.

The patent introduces dynamic execution paths where threads can transition between different execution segments based on control flow conditions. Threads are no longer statically bound to a single lock-step execution path but can dynamically join different warp groups and execute different code paths, maintaining high utilization while managing complexity.

The patent extracts the active threads from the waiting threads by forming separate warp groups. Only the active threads in each warp group execute instructions during their respective time slices, while waiting threads are excluded from execution. This eliminates redundant calculations for waiting threads while maintaining simplified program counter management within each active warp group.

The patent implements periodic execution where different warp groups are activated in alternating time slices. Each warp group executes periodically during its designated time slice, allowing threads to be active only when needed rather than continuously executing redundant operations. This periodic activation pattern reduces redundant calculations while maintaining manageable program counter state.

The patent applies local quality by performing register promotion at the warp group level rather than requiring uniform promotion across all threads. Each warp group can have its own set of promoted registers tailored to its specific access pattern. This allows flexible data access with non-constant indices while managing register promotion complexity locally within each warp group rather than globally across all threads.

The patent performs preliminary register promotion for each warp group before execution, analyzing the specific access patterns of that warp group and pre-loading necessary data into registers. This preliminary action allows flexible non-constant indexing during execution while the complexity of register promotion is resolved in advance for each specific warp group's access pattern.