GPU Reprojection Error Handling via DRAM Fallback

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Solution Overview

Problem

Reprojection operations in graphics processing units (GPUs) often take longer than desired timelines, leading to delayed data reads, incorrect data display, excessive bandwidth usage, and visual artifacts in augmented reality (AR) and virtual reality (VR) applications.

Innovation Solution

The solution involves modifying the data read or retrieval process to handle delayed reprojection by reading from dynamic random access memory (DRAM) instead of system caches, using error handling mechanisms to retrieve data from alternate locations, and configuring buffers to display correct data, thereby reducing bandwidth and visual artifacts.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If data is read from system caches during reprojection operations, then data retrieval speed is improved, but data accuracy deteriorates when reprojection is delayed

Engineering Contradiction:
Improvedata retrieval speedVSAvoiddata accuracy
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent implements a timeline validation mechanism that checks whether the reprojection operation completed before the display deadline. If the reprojection is delayed beyond the timeline, the system proactively invalidates the cache data and retrieves fresh data from DRAM, preventing the display of stale or incorrect data. This preliminary validation and conditional data retrieval ensures data accuracy while maintaining efficient cache usage under normal conditions.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If data is repeatedly read from DRAM due to reprojection delays, then data accuracy is improved, but bandwidth consumption increases

Engineering Contradiction:
Improvedata accuracyVSAvoidbandwidth consumption
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent implements a feedback mechanism where the display processor monitors the completion status of reprojection operations against display deadlines. When a reprojection delay is detected, the system triggers an invalidate operation on the cache and a conditional read from DRAM. This feedback-driven approach ensures that DRAM reads occur only when necessary (when reprojection is delayed), maintaining data accuracy while minimizing unnecessary bandwidth consumption that would occur with continuous or preventive DRAM reads.

Inventive Principle:
Principle #23Feedback

3Reliability

If error handling mechanisms are added to detect reprojection delays, then data accuracy is improved, but system complexity increases

Engineering Contradiction:
Improvedata accuracyVSAvoidsystem complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces a timeline validation mechanism as an intermediary layer between the reprojection operation and the display output. This mechanism compares the reprojection completion timestamp against the display deadline and conditionally triggers cache invalidation and data retrieval operations. By using this intermediary validation step, the system achieves robust error handling with minimal additional complexity, avoiding the need for complex error detection algorithms or multiple redundant systems.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20240386980A1Error handling for reprojection timeline
Publication Date: 2024.11.21 QUALCOMM INC
  • US20240386980A1 patent drawing
  • US20240386980A1 patent drawing
  • US20240386980A1 patent drawing

AI summary

Aspects presented herein relate to methods and devices for data or graphics processing including an apparatus, e.g., a graphics processing unit (GPU). The apparatus may obtain an indication of a data write for data associated with data processing. The apparatus may write, based on the indication, the data associated with the data processing to a memory address. The apparatus may receive a read request for the data including the memory address, where the read request is associated with a read with invalidate process. The apparatus may retrieve, based on the read request, the data from at least one of a first cache or at least one second memory, where the retrieval of the data is based on a timing of the indication of the data write. The apparatus may output the retrieved data from at least one of the first cache or the at least one second memory.