GPU Restart Index Skipping in Tile-Based Deferred Rendering
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Solution Overview
Problem
Conventional GPU architectures face performance issues and limited throughput due to the handling of restart indices during tile-based deferred rendering (TBDR), particularly in sliced GPU architectures, where the presence of a restart index necessitates sequential index fetching and primitive assembly, impacting efficiency.
Innovation Solution
A GPU is configured to determine the location of a restart index during a tile sorting pass and calculate a skip count to bypass fetching the restart index during the tile rendering pass, enabling parallel index fetching and primitive assembly by generating visibility data based on the skip count and primitive topology.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the GPU marks all primitives as visible after detecting a restart index during the tile sorting pass, then the primitives can be assembled correctly in the tile rendering pass, but invisible primitives are processed unnecessarily, reducing GPU performance
Solution Approach 1:
The patent applies preliminary action by determining the skip count during the tile sorting pass, before the tile rendering pass begins. The GPU calculates how many indices to skip after encountering a restart index and stores this information in the visibility data. This allows the tile rendering pass to directly skip the appropriate number of indices without processing invisible primitives, thus maintaining both correctness and performance.
2Reliability
If the GPU fetches the restart index and all subsequent indices from the index buffer to assemble primitives correctly, then the primitive topology is preserved, but the processing time increases due to sequential operations
Solution Approach 1:
The patent extracts the restart index handling logic from the main primitive assembly process. By identifying the restart index location during the tile sorting pass and calculating the skip count, the patent separates the restart index processing from the main rendering pipeline. This allows the tile rendering pass to skip directly to the relevant indices without fetching and processing the restart index itself, thus preserving topology while reducing processing time.
Solution Approach 2:
The patent performs preliminary calculation of the skip count during the tile sorting pass, determining exactly how many indices to skip before the tile rendering pass begins. This advance preparation eliminates the need for sequential index fetching during rendering, as the GPU can directly jump to the correct indices using the pre-calculated skip count stored in the visibility data.
3Productivity
If the GPU implements parallel index fetching and primitive assembly in a sliced architecture, then throughput is improved, but the presence of a restart index forces sequential processing, limiting throughput
Solution Approach 1:
The patent resolves the architecture conflict by performing preliminary calculation of the skip count during the tile sorting pass. This advance determination of how many indices to skip allows the sliced GPU architecture to maintain parallel index fetching and primitive assembly operations, as the restart index handling is resolved before the parallel processing begins in the tile rendering pass.
Data Source
AI summary
Efficiently handling restart indices during tile-based deferred rendering (TBDR) by graphics processing units (GPUs) is disclosed herein. In some aspects, a processor circuit of a GPU determines, during a tile sorting pass, a location of a restart index in a plurality of indices of an index buffer associated with a primitive topology, and determines a skip count indicating a number of indices to skip during a tile rendering pass, based on the primitive topology and the location of the restart index. In some aspects, the processor circuit also determines visibility statuses corresponding to primitives of the primitive topology, and generates visibility data comprising the visibility statuses and the skip count. Subsequently, during the tile rendering pass, the processor circuit bypasses fetching of the restart index, based on the skip count. According to some aspects, the processor circuit may also assemble the primitives based on the visibility data.