GPU Trust Architecture With Multiple Roots And Runtime Attestation

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Solution Overview

Problem

Current graphics processing units (GPUs) face challenges in efficiently processing graphics data due to limitations in parallel processing capabilities and security vulnerabilities, particularly in environments requiring high trust and integrity.

Innovation Solution

Implementing a graphics processing unit (GPU) with multiple roots of trust (RoTs) and runtime attestation to enhance security and performance by ensuring secure I/O operations and isolating compute resources, using a Trusted Execution Environment (TEE)-I/O support and encryption keys for data protection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If graphics processors use fixed function computational units, then processing reliability is improved, but processing versatility deteriorates

Engineering Contradiction:
Improveprocessing reliabilityVSAvoidprocessing versatility
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The graphics processor is divided into multiple independent computational units, each with dedicated security attributes and trust zones. This segmentation allows different units to handle different types of operations with appropriate security levels, maintaining reliability for critical functions while enabling versatility through specialized units for various graphics operations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A security management unit acts as an intermediary between computational units and external resources, managing security policies, encryption keys, and access controls. This intermediary enables versatile operations while maintaining reliable security boundaries through centralized policy enforcement.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Speed

If graphics processors implement pipelining and SIMT architecture, then processing speed is improved, but security vulnerability increases

Engineering Contradiction:
Improveprocessing speedVSAvoidsecurity vulnerability
Core Design Contradiction:
SpeedVSObject-affected harmful factors

Solution Approach 1:

The pipelined architecture is segmented into multiple trust zones with isolated security contexts. Each pipeline stage can be assigned different security attributes, allowing high-speed parallel processing while preventing security vulnerabilities from propagating across the entire pipeline through enforced boundaries.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different segments of the pipeline are assigned different security qualities and protection levels based on their specific functions. Critical stages handling sensitive data receive enhanced security measures, while less critical stages maintain standard protection, optimizing both speed and security vulnerability resistance.

Inventive Principle:
Principle #3Local quality

3Productivity

If multiple threads execute synchronously in SIMT architecture, then productivity is improved, but trust verification complexity increases

Engineering Contradiction:
Improveprocessing productivityVSAvoidtrust verification complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

Each thread in the SIMT architecture is automatically assigned security attributes and trust verification is performed through self-service mechanisms where threads present their security credentials. This maintains high productivity through parallel execution while reducing verification complexity through automated security management.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

A universal security attribute system is implemented that works across all threads and computational units. This multi-functional security framework handles diverse trust verification scenarios with a unified approach, reducing complexity compared to separate verification mechanisms for each thread.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250292353A1Graphics data processing trust using multiple roots of trust and runtime attestation
Publication Date: 2025.09.18 INTEL CORP
  • US20250292353A1 patent drawing
  • US20250292353A1 patent drawing
  • US20250292353A1 patent drawing

AI summary

An apparatus to facilitate graphics data processing trust using multiple roots of trust and runtime attestation is disclosed. The apparatus includes a graphics processor to: collect, using a hardware root-of-trust (RoT), first measurements from a physical partition manager (PPM); generate, using the first measurements, a PPM compound device identifier (CDI) to securely bind to the PPM; collect, using the PPM, second measurements from a logical partition manager (LPM); generate, using the second measurements and the PPM CDI, a LPM CDI to securely bind to the LPM; collect, using the LPM, third measurements from a graphics tenant partition of the graphics processor, the graphics tenant partition comprises a confidential compute (CC) environment to run a workload of a host tenant partition; and generate, using the third measurements and the LPM CDI, a GPUN-TDn CDI for the graphics tenant partition to be securely bound to the graphics tenant partition.