Heavy-Weight Light-Weight GPU Shader Core Pair Architecture

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Solution Overview

Problem

Existing GPU shader core performance enhancement methods, such as replicating processing engines (PEs), result in increased size and area, which is inefficient.

Innovation Solution

A shader core design that includes a combination of heavy-weight and light-weight PEs, with a shared register file and warp sequencer unit, allowing instruction traces to be scheduled based on trace headers, enabling efficient execution without doubling the size of the shader core.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the number of PEs is increased by replicating PEs, then the performance of the GPU is improved, but the overall size and area of the shader core increases

Engineering Contradiction:
ImproveGPU performanceVSAvoidshader core area
Core Design Contradiction:
ProductivityVSArea of stationary object

Solution Approach 1:

The patent applies local quality by creating heterogeneous PE pairs where each PE has different execution unit configurations. Heavy-weight PEs contain all execution unit types while light-weight PEs contain only frequently-used execution units. This allows the system to optimize for common workloads using compact light-weight PEs while maintaining the capability to handle diverse workloads through heavy-weight PEs, thereby improving performance without proportionally increasing area.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the configuration parameters of PEs by varying the number and types of execution units in different PEs. Instead of replicating identical PEs, the system uses parameter changes to create PEs with different execution unit compositions based on workload requirements, achieving better performance per unit area by matching PE capabilities to instruction trace characteristics.

Inventive Principle:
Principle #35Parameter changes

2Area of stationary object

If light-weight PEs with fewer execution units are used, then the area of the shader core is reduced, but the capability to execute diverse instruction traces is limited

Engineering Contradiction:
Improveshader core areaVSAvoidinstruction trace execution capability
Core Design Contradiction:
Area of stationary objectVSAdaptability or versatility

Solution Approach 1:

The patent segments the PE population into light-weight and heavy-weight PEs that work together in pairs. Light-weight PEs handle common, frequently-executed instruction traces, while heavy-weight PEs are available to handle diverse or complex instruction traces that require additional execution unit types. This segmentation allows the system to maintain small average PE size while preserving full execution capability when needed.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements universality through the heavy-weight PE which contains all types of execution units and can execute any instruction trace. The light-weight PE, while more specialized, covers the most common cases. Together, the pair provides universal functionality, ensuring that any instruction trace can be executed by at least one PE in the pair, thus maintaining adaptability without requiring every PE to have full capabilities.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11120603B2Heavy-weight/light-weight GPU shader core pair architecture
Publication Date: 2021.09.14 SAMSUNG ELECTRONICS CO LTD
  • US11120603B2 patent drawing
  • US11120603B2 patent drawing
  • US11120603B2 patent drawing

AI summary

A shader core includes a first processing element (PE), a second processing element, a register file and a warp sequencing unit. The first PE includes a first predetermined number of execution units, and the second PE includes a second predetermined number of execution units in which the second predetermined number of execution units is less than the first predetermined number of execution units. The register file shared by the first PE and the second PE. The warp sequencer unit (WSQ) is coupled to the first PE and to the second PE and schedules an instruction trace to execute on the first PE or the second PE based on information contained in a trace header of the instruction trace. The information contained in the trace header indicates whether the instruction trace is executable on the second PE.