GPU Shared Local Memory Bank Conflict Arbitration

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Solution Overview

Problem

Existing graphics processing technologies face inefficiencies in shared local memory access due to bank conflicts, which reduce bandwidth and utilization, as multiple threads accessing the same bank require serialization, leading to underutilization of bank ports.

Innovation Solution

Implementing a per-bank port arbitration scheme that examines SIMD messages from multiple threads simultaneously, allowing for the merging of requests and scheduling of read and write operations independently, even if they map to the same bank, thereby reducing bank conflicts and maximizing port utilization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If multiple threads access the same SLM bank simultaneously, then memory bandwidth is increased, but bank conflicts occur reducing effective bandwidth

Engineering Contradiction:
Improvememory bandwidthVSAvoideffective bandwidth
Core Design Contradiction:
PowerVSReliability

Solution Approach 1:

The SLM is divided into multiple banks, and the arbitration logic segments the access requests by routing them to specific banks based on address mapping. This segmentation allows parallel access to different banks while avoiding conflicts within the same bank.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a new dimension of arbitration by examining SIMD messages from multiple threads simultaneously across different thread dimensions. The per-bank port arbitration scheme adds a temporal dimension by scheduling read and write operations independently, even when they map to the same bank, thereby resolving conflicts in the time dimension rather than just spatial distribution.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If bank access is serialized to avoid conflicts, then bank utilization is improved, but throughput decreases

Engineering Contradiction:
Improvebank utilizationVSAvoidthroughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The arbitration logic performs preliminary examination of SIMD messages from multiple threads before actual memory access. By predicting and pre-scheduling access patterns, the system can prepare arbitration decisions in advance, reducing actual access latency and maintaining high throughput.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The per-bank port arbitration scheme ensures continuous utilization of bank ports by independently scheduling read and write operations. Even when conflicts are detected, the system maintains continuous useful action by switching between threads and operations rather than serializing all accesses, thereby keeping throughput high while maintaining proper bank utilization.

Inventive Principle:
Principle #20Continuity of useful action

3Reliability

If per-bank port arbitration examines multiple threads simultaneously, then bank utilization increases, but arbitration complexity increases

Engineering Contradiction:
Improvebank utilizationVSAvoidarbitration complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The arbitration logic is segmented into per-bank components, where each bank has its own arbitration unit. This segmentation distributes the complexity across multiple independent units rather than requiring a single complex centralized arbiter, making the overall system more manageable and scalable.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The arbitration scheme is dynamic in that it adapts its behavior based on the specific access patterns of different threads. The logic dynamically selects which threads to examine and how to schedule operations based on real-time conditions, allowing it to handle multiple threads simultaneously without requiring exhaustive examination of all possible combinations.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10089115B2Apparatus to optimize GPU thread shared local memory access
Publication Date: 2018.10.02 INTEL CORP
  • US10089115B2 patent drawing
  • US10089115B2 patent drawing
  • US10089115B2 patent drawing

AI summary

One embodiment provides for a graphics processor comprising first logic coupled with a first execution unit, the first logic to receive a first single instruction multiple data (SIMD) message from the first execution unit; second logic coupled with a second execution unit, the second logic to receive a second SIMD message from the second execution unit; and third logic coupled with a bank of shared local memory (SLM), the third logic to receive a first request to access the bank of SLM from the first logic, a second request to access the bank of SLM from the second logic, and in a single access cycle, schedule a read access to a read port for the first request and a write access to a write port for the second request.