Selective Soft Error Hardening for GPU Circuit Components
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Solution Overview
Problem
Computer architectures, particularly graphic processing units (GPUs), face challenges in mitigating soft errors due to their large number of execution units and registers, making conventional hardening techniques impractical, and existing methods focus on binary error detection without considering the magnitude of output errors.
Innovation Solution
The approach involves selectively hardening specific gates or memory cells based on the quantitative assessment of soft error impact on output word magnitude, prioritizing resources by ranking gates or memory cells according to their contribution to output error, and applying soft error hardening circuitry only to those that significantly affect the results, using bit-shifting to align significant bits with protected positions for precise error mitigation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional hardening techniques (increasing circuit size, adding redundant circuits) are applied to GPUs, then soft error resistance is improved, but device area and complexity increase significantly
Solution Approach 1:
The patent applies selective hardening only to specific gates and memory cells that are most susceptible to soft errors and have the greatest impact on output correctness. Instead of uniformly hardening the entire GPU circuit, the invention identifies critical components through simulation and applies hardening resources locally where they provide maximum benefit, thereby reducing overall device complexity while maintaining soft error resistance.
Solution Approach 2:
The patent segments the GPU circuit into individual gates and memory cells, evaluating each component's susceptibility to soft errors separately. This segmentation allows the system to identify and harden only the specific components that require protection, rather than treating the entire circuit as a single unit, thus reducing the overall complexity of hardening implementation.
2Loss of energy
If selective hardening based on error magnitude assessment is implemented, then hardening overhead is reduced, but measurement and analysis complexity increases
Solution Approach 1:
The patent performs preliminary simulation and analysis during the design phase to assess the impact of soft errors on each gate and memory cell before the actual hardening implementation. By conducting this error magnitude assessment in advance, the system can identify which components require hardening without requiring complex real-time measurement mechanisms during operation, thus reducing hardening overhead while managing analysis complexity through upfront evaluation.
Data Source
AI summary
Hardening of an integrated circuit such as a GPU processor to soft errors caused by particle strikes is applied selectively to the set of devices according to the magnitude of error resulting from this soft error for the particular device. This approach differs from approaches that protect all devices, all devices likely to produce an output error, or all devices that are vulnerable.