GPU Sort Middle Architecture for Parallel Workload Distribution

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Solution Overview

Problem

Current graphics processing units (GPUs) face limitations in efficiently processing graphics data due to reliance on fixed function computational units and lack of parallel processing capabilities for general-purpose operations, which hinders performance in tasks like machine learning and pattern analysis.

Innovation Solution

A GPU architecture with a parallel processing unit that includes a scheduler, processing clusters, and a memory crossbar, enabling efficient distribution of workloads across multiple processing clusters and supporting general-purpose parallel compute operations, including graphics processing, machine learning, and pattern analysis.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If fixed function computational units are used in graphics processors, then graphics processing operations can be performed, but the processor cannot support a wider variety of operations for processing vertex and fragment data

Engineering Contradiction:
Improvevariety of operationsVSAvoidcomputational units
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements a general-purpose graphics processing unit with a unified architecture that can execute both traditional graphics operations and general-purpose compute tasks. The processing clusters contain execution units capable of performing diverse operations including vertex processing, fragment processing, and machine learning workloads, allowing a single hardware design to serve multiple functions rather than requiring separate dedicated units for each operation type

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If parallel processing is implemented to increase performance, then processing efficiency improves, but the architecture complexity increases

Engineering Contradiction:
Improveprocessing efficiencyVSAvoidarchitecture
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent divides the processing system into multiple independent processing clusters, each containing execution units, register files, and load/store units. This segmentation allows parallel execution of multiple threads and workloads simultaneously while maintaining modular architecture that simplifies design and management. Each processing cluster can operate independently, enabling scalable parallel processing without requiring complete redesign of the entire system

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements nested memory hierarchies where processing clusters access shared memory through a memory crossbar structure. The memory system is organized with multiple ports that can simultaneously serve different processing clusters, creating a nested access pattern that enables efficient parallel memory operations without requiring separate memory subsystems for each cluster, thereby reducing overall architectural complexity

Inventive Principle:
Principle #7Nested doll (Nesting)

3Productivity

If multiple processing clusters are used to maximize parallel processing, then throughput increases, but data distribution and coordination become more complex

Engineering Contradiction:
ImprovethroughputVSAvoiddata distribution
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent introduces a memory crossbar as an intermediary structure between processing clusters and shared memory. This crossbar provides multiple ports that can simultaneously connect to different processing clusters, enabling efficient data distribution without requiring complex routing logic. The crossbar acts as a mediator that handles data routing and coordination between multiple clusters, simplifying the data distribution problem while maintaining high throughput parallel processing capability

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentEP4109390A1Sort middle architecture for multiple graphics processing units
Publication Date: 2022.12.28 INTEL CORP
  • EP4109390A1 patent drawingFigure 1
  • EP4109390A1 patent drawingFigure 2A
  • EP4109390A1 patent drawingFigure 2B

AI summary

Methods, systems and apparatuses may provide for technology that generates, with a first graphics processing unit, geometric attributes associated with a first primitive. The technology determines that the first primitive is associated with a second graphics processing unit based on a first screen space tile associated with the first primitive, and transfers the geometric attributes of the first primitive from the first graphics processing unit to the second graphics processing unit based on the first primitive being associated with the first screen space tile.