GPU Sparse Compute Scheduling for Arbitrary Neural Networks
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Solution Overview
Problem
Current graphics processing units struggle to efficiently handle arbitrary neural networks due to inefficiencies in processing sparse matrices, leading to suboptimal performance in parallel computing tasks.
Innovation Solution
Implementing a graphics processing unit with a data management unit that includes a scheduler for matrix operations, active logic for tracking active operands, and skip logic for unimportant operands, coupled with processing circuitry that includes a plurality of processing elements for efficient sparse matrix processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional fixed function computational units are used for graphics data processing, then processing speed is maintained, but adaptability to arbitrary neural networks deteriorates
Solution Approach 1:
The graphics processing unit is designed with a universal data management unit that can handle both traditional graphics data and arbitrary neural network operations. The scheduler, active logic, and skip logic components work together to provide a unified processing framework that adapts to different computational requirements, enabling the same hardware to perform both graphics rendering and neural network inference efficiently.
Solution Approach 2:
The processing system employs dynamic scheduling mechanisms where the scheduler can adaptively allocate processing resources based on the specific requirements of the neural network operation. The active logic dynamically identifies and processes only the necessary operands, while skip logic dynamically bypasses unnecessary computations, allowing the system to optimize performance for different neural network architectures and sparsity patterns.
2Productivity
If dense matrix processing is used for neural networks, then computational completeness is maintained, but resource utilization deteriorates due to processing unnecessary zero elements
Solution Approach 1:
The system extracts and processes only the non-zero elements of sparse matrices through the active logic component. The skip logic identifies zero elements and bypasses them entirely, removing unnecessary computational steps from the processing pipeline. This extraction approach maintains computational completeness for the relevant data while eliminating waste on zero elements.
Solution Approach 2:
The processing approach applies different quality levels to different parts of the matrix data. Non-zero elements receive full processing attention through the active logic, while zero elements are handled with minimal processing through the skip logic. This local differentiation in processing quality optimizes resource utilization by concentrating computational effort where it is actually needed.
3Productivity
If all operands are processed in parallel, then processing throughput is maximized, but computational overhead deteriorates due to synchronization requirements
Solution Approach 1:
The skip logic component enables the processor to rush through zero elements without performing full processing operations. By identifying and skipping these elements, the system reduces the number of synchronization points required and minimizes computational overhead while maintaining high throughput for the essential non-zero elements through parallel processing.
Solution Approach 2:
The system applies partial processing action to zero elements (skipping them entirely) and full processing action to non-zero elements. This selective application of processing intensity optimizes the balance between throughput and overhead, avoiding the excessive synchronization requirements that would result from applying full processing to all elements including zeros.
Data Source
AI summary
An apparatus to facilitate processing of a sparse matrix for arbitrary graph data is disclosed. The apparatus includes a graphics processing unit having a data management unit (DMU) that includes a scheduler for scheduling matrix operations, an active logic for tracking active input operands, and a skip logic for tracking unimportant input operands to be skipped by the scheduler. Processing circuitry is coupled to the DMU. The processing circuitry comprises a plurality of processing elements including logic to read operands and a multiplication unit to multiply two or more operands for the arbitrary graph data and customizable circuitry to provide custom functions.