GPU Sparse Matrix Detection Unit for Register Conflict Reduction
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Solution Overview
Problem
Traditional GPUs experience performance reduction and increased power consumption due to high read and write conflicts in the register file during matrix calculations, and fail to leverage the sparsity of matrices for acceleration.
Innovation Solution
A graphics processing unit is designed with a sparse matrix detection unit, assertion register, and matrix calculation unit that identifies and ignores zero matrices, allowing only non-zero matrices to be calculated, thereby reducing unnecessary computations and data access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the matrix calculation unit reads data directly from the register file, then the matrix calculation can be performed, but the read and write requirements for the register file are very high, causing read and write conflicts that reduce computing performance
Solution Approach 1:
The patent segments the matrix data storage by separating zero matrices from non-zero matrices. The register file is divided into multiple banks, with some banks storing only non-zero matrices. This segmentation reduces the access complexity by allowing the matrix calculation unit to directly access specific banks without scanning entire register files, thereby reducing read/write conflicts while maintaining calculation performance.
Solution Approach 2:
The patent implements preliminary action by pre-processing matrix data before it enters the register file. A matrix data preprocessing unit identifies and separates zero matrices from non-zero matrices before storage. This preliminary classification enables the matrix calculation unit to skip zero matrices entirely, reducing the number of read operations required and decreasing register file access complexity.
2Reliability
If the matrix calculation unit processes all matrices including zero matrices, then complete matrix calculation is performed, but power consumption increases and matrix calculation time increases due to unnecessary computations
Solution Approach 1:
The patent extracts zero matrices from the processing stream by implementing a preprocessing mechanism that identifies matrices with all-zero elements before they enter the calculation pipeline. These zero matrices are extracted and excluded from further processing. This ensures calculation completeness for non-zero matrices while eliminating wasteful power consumption associated with processing zero matrices.
Solution Approach 2:
The patent changes the parameter of matrix data representation by introducing a flag or metadata indicator that marks whether a matrix contains non-zero elements. This parameter change enables the matrix calculation unit to quickly determine whether to process a matrix based on its content characteristics, thereby reducing power consumption without compromising the reliability of calculations for matrices that require processing.
3Reliability
If the matrix calculation unit processes all matrices including zero matrices, then all data is processed, but matrix calculation time increases due to unnecessary computations on zero matrices
Solution Approach 1:
The patent performs preliminary classification of matrices into zero and non-zero categories before the main calculation phase. This preliminary action creates an optimized execution path where the matrix calculation unit only processes non-zero matrices, significantly reducing calculation time while maintaining completeness through the preprocessing stage that ensures no non-zero matrices are missed.
Solution Approach 2:
The patent implements a skipping mechanism where the matrix calculation unit can rapidly skip over zero matrices identified by preprocessing or metadata flags. This allows the calculation unit to rush through unnecessary data without performing full computational operations, thereby reducing overall matrix calculation time while maintaining calculation completeness for relevant data.
Data Source
AI summary
A graphics processing unit includes a sparse matrix detection unit, a register file, an assertion register, and a matrix calculation unit. The sparse matrix detection unit reads a plurality of matrices from a storage device and determines whether the matrices are zero matrices or non-zero matrices to output a determination result. The register file stores the plurality of matrices from the sparse matrix detection unit. The assertion register marks up the matrices according to the determination result, and outputs a mark result. The matrix calculation unit receives a matrix calculation instruction, reads the non-zero matrices in the plurality of matrices from the register file according to the mark result, and calculates the non-zero matrices.