Dynamic State Register Copy for GPU Shader Load Balancing

The patent merges separate vertex shader and pixel shader cores into a unified shader core that can execute both vertex and pixel shader programs. This consolidation allows a single core to handle both types of operations, eliminating the load imbalance problem that occurred when separate cores were used, as one core could be fully utilized regardless of whether vertex or pixel operations dominated the workload.

The unified shader core is designed with multi-functionality to execute both vertex shader and pixel shader programs. By making the core universal rather than specialized, it can adapt to varying workload compositions and maintain high utilization across different application scenarios, whether vertex-intensive or pixel-intensive.

The patent segments the centralized master register into multiple per-thread state registers, with each thread having its own dedicated state storage. This segmentation eliminates contention for state access, as each thread can read and write its own state information independently without blocking other threads, while still maintaining organized state management through the register structure.

Each thread is equipped with its own state registers that it can access directly without needing to contend with other threads. This self-service approach allows threads to independently manage their own state information, improving access speed while maintaining the organizational benefits of register-based state storage.