Software State Set Allocation for GPU Context Switching

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Solution Overview

Problem

Current graphics processing units (GPUs) face challenges in efficiently managing processor states due to coarse granularity context switching, which affects the execution of graphics pipeline instructions dependent on various context-specific constants.

Innovation Solution

A system and method for controlling state sets from software, where a processor detects and executes commands to allocate, reserve, and use state sets within its execution unit, allowing for context switching without external memory access, using on-chip storage for reserved state sets and content addressable memory to manage state set IDs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If coarse granularity context switching is used in GPU, then device complexity is reduced, but productivity deteriorates due to inefficient state management

Engineering Contradiction:
Improveprocessing efficiencyVSAvoidstate management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the monolithic state management into discrete state sets that can be independently allocated, reserved, and switched. Each state set represents a distinct context configuration, allowing fine-grained control over processor states without requiring complex global state management mechanisms.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements preliminary action by pre-allocating and pre-reserving state sets before they are needed for execution. State sets are prepared in advance and stored in on-chip memory, enabling rapid context switching without requiring state management operations during critical execution paths.

Inventive Principle:
Principle #10Preliminary action

2Speed

If on-chip storage is used for state sets, then speed is improved by avoiding external memory access, but device complexity increases

Engineering Contradiction:
Improvecontext switching speedVSAvoidon-chip storage management
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent uses copying by creating duplicate copies of state data and storing them in on-chip memory buffers. Instead of accessing external memory during context switching, the system copies state sets into fast on-chip storage, enabling rapid retrieval and switching while maintaining data integrity through the copy mechanism.

Inventive Principle:
Principle #26Copying

3Reliability

If state sets are reserved and protected from modification, then reliability is improved, but device complexity increases due to management overhead

Engineering Contradiction:
Improvestate integrityVSAvoidreservation management
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements self-service by enabling software to autonomously manage state set reservations and allocations through programmable interfaces. The system allows software to automatically track, reserve, and manage state sets without requiring complex hardware enforcement mechanisms, shifting the management burden to the software layer while maintaining reliability through software-controlled protection.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS10180789B2Software control of state sets
Publication Date: 2019.01.15 ADVANCED MICRO DEVICES INC
  • US10180789B2 patent drawing
  • US10180789B2 patent drawing
  • US10180789B2 patent drawing

AI summary

Systems, apparatuses, and methods for implementing software control of state sets are disclosed. In one embodiment, a processor includes at least an execution unit and a plurality of state registers. The processor is configured to detect a command to allocate a first state set for storing a first state, wherein the command is generated by software, and wherein the first state specifies values for the plurality of state registers. The command is executed on the execution unit while the processor is in a second state, wherein the second state is different from the first state. The first state set of the processor is allocated with the first state responsive to executing the command on the execution unit. The processor is configured to allocate the first state set for the first state prior to the processor entering the first state.