GPU Surface State Access via 64-bit Virtual Addresses

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Solution Overview

Problem

Current graphics processing units (GPUs) face performance penalties due to the need to flush the pipeline when changing heap-based state settings outside of command list boundaries, particularly in multi-threaded applications, leading to inefficiencies in accessing surface and sampler states.

Innovation Solution

Implementing a memory access technique using 64-bit virtual addresses to access surface and sampler states, eliminating the reliance on heap-based state programming and thereby avoiding pipeline flushes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If heap-based state programming is used for surface and sampler state, then state changes can be made, but pipeline flush is required which causes significant performance penalty

Engineering Contradiction:
Improvestate change capabilityVSAvoidpipeline throughput
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent introduces a virtual address space as an intermediary layer between the CPU and GPU heap-based state programming. This virtual address space acts as a mediator that translates CPU memory accesses into GPU-friendly state changes without requiring pipeline flushes, thereby resolving the contradiction between state change capability and pipeline throughput.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent replaces the mechanical pipeline flushing mechanism with a virtual memory addressing system. Instead of relying on the GPU pipeline to flush and resync after heap-based state changes, the system uses virtual addresses to directly access surface and sampler states, eliminating the need for pipeline flush operations and maintaining continuous throughput.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Ease of operation

If explicit state parameters are programmed into hard coded data structures, then state settings can be configured, but changes require pipeline drain which introduces performance penalty

Engineering Contradiction:
Improvestate configurationVSAvoidpipeline drain time
Core Design Contradiction:
Ease of operationVSLoss of time

Solution Approach 1:

The patent transforms the static hard-coded data structure approach into a dynamic virtual address space system. Instead of configuring states through rigid, fixed-location data structures that require pipeline draining for changes, the system uses dynamic virtual addresses that can be directly modified without time-consuming pipeline drain operations, thereby improving ease of operation while reducing time loss.

Inventive Principle:
Principle #15Dynamics

3Extent of automation

If multi-threaded applications access surface and sampler states, then parallel processing is enabled, but pipeline flush is required for state changes causing inefficiency

Engineering Contradiction:
Improvemulti-threaded processingVSAvoidthread execution efficiency
Core Design Contradiction:
Extent of automationVSProductivity

Solution Approach 1:

The patent creates a universal virtual address space that serves multiple threads simultaneously. This unified addressing mechanism allows different threads to access and modify surface and sampler states independently through virtual addresses, enabling multi-threaded processing without requiring pipeline flushes for each thread's state changes, thereby maintaining high productivity across all threads.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20240231621A9Virtual address access to GPU surface and sampler states
Publication Date: 2024.07.11 INTEL CORP
  • US20240231621A9 patent drawing
  • US20240231621A9 patent drawing
  • US20240231621A9 patent drawing

AI summary

Embodiments described herein provide a technique to enable access to entries in a surface state or sampler state using 64-bit virtual addresses. One embodiment provides a graphics core that includes memory access circuitry configured to facilitate access to the memory by functional units of the graphics core. The memory access circuitry is configured to receive a message to access an entry in a surface state or a sampler state associated with a parallel processing operation. The message specifies a base address for a surface state entry or sampler state entry. The circuitry can add the base address and the offset to determine a 64-bit virtual address for the entry in the surface state entry or the sampler state and submit a memory access request to the memory to access the entry of the surface state or sampler state.