GPU Thread Merging for Tile-Based Rendering Efficiency

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Solution Overview

Problem

Conventional GPUs using SIMD architecture face inefficiencies in vertex shader computation due to granular allocation of threads, leading to increased memory usage and bandwidth requirements in tile-based rendering.

Innovation Solution

Implementing a method for graphics-processing units (GPUs) to merge threads based on specific conditions, such as shared draw calls, identical shader code assemblies, and hardware settings, allowing for optimized computation of vertex varyings and efficient resource allocation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If threads are allocated granularly in SIMD architecture, then thread parallelism is achieved, but shader efficiency decreases and memory usage increases

Engineering Contradiction:
Improveshader efficiencyVSAvoidmemory usage
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent merges multiple threads into a thread group when they share the same draw call, allowing these threads to execute the same shader code assembly together. This merging reduces the number of separate thread allocations needed, thereby decreasing memory usage and bandwidth requirements while maintaining shader execution efficiency through consolidated resource management.

Inventive Principle:
Principle #5Merging (Combining)

2Ease of operation

If threads are allocated granularly in SIMD architecture, then individual thread execution is enabled, but memory bandwidth consumption increases

Engineering Contradiction:
Improvethread execution flexibilityVSAvoidmemory bandwidth consumption
Core Design Contradiction:
Ease of operationVSUse of energy by moving object

Solution Approach 1:

Threads belonging to the same draw call are merged into a thread group, causing them to execute the same shader code assembly in a consolidated manner. This reduces redundant memory access operations and bandwidth consumption, as the merged threads share common execution resources and data paths rather than accessing memory independently.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The thread group structure enables a single execution unit to handle multiple threads that share the same draw call characteristics. This multi-functional approach allows the GPU to process multiple threads efficiently using shared resources, reducing overall memory bandwidth consumption while maintaining execution flexibility.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Quantity of substance

If threads are merged based on draw call information, then memory efficiency improves, but thread management complexity increases

Engineering Contradiction:
Improvememory usageVSAvoidthread management complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The system performs preliminary classification of threads into draw call groups before execution. By pre-organizing threads based on their draw call affiliation and shader code assembly identity, the system simplifies subsequent thread management operations. This preliminary grouping enables efficient thread merging decisions without requiring complex real-time analysis during execution.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9830731B2Methods of a graphics-processing unit for tile-based rendering of a display area and graphics-processing apparatus
Publication Date: 2017.11.28 MEDIATEK INC
  • US9830731B2 patent drawing
  • US9830731B2 patent drawing
  • US9830731B2 patent drawing

AI summary

A method of a graphics-processing unit (GPU) for tile-based rendering of a display area and a graphics-processing apparatus are provided. The method includes the steps of computing vertex positions of a plurality of vertexes, wherein the first vertex corresponds to a first thread and the second vertex corresponds to a second thread; determining whether a thread merge condition is satisfied; merging the first thread and the second thread to a thread group when determining that the thread merge condition is satisfied; computing vertex varyings of the plurality of vertexes, wherein when the first thread and the second thread are merged to the thread group, a varying of the first vertex and a varying of the second vertex are computed with respect to a program counter.