GPU Tile Cache Allocation for Multi-VM Graphics Virtualization
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Solution Overview
Problem
Existing GPU virtualization technologies face challenges in efficiently sharing graphics memory resources among multiple virtual machines, leading to inefficiencies and performance bottlenecks, particularly in systems requiring near-native graphics performance.
Innovation Solution
A method and apparatus for efficient graphics virtualization that employs intelligent allocation of tile caches and shared local memory between virtual machines, utilizing spillover into system memory and buffering to reduce blocking, along with intelligent arbitration to optimize resource utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If shadow page tables are implemented to support multiple VMs sharing a physical GPU, then multiple VMs can access the GPU simultaneously, but memory usage increases and translation overhead increases
Solution Approach 1:
The patent merges the shadow page table functionality into the IOMMU translation cache by using the same translation cache structure to serve both IOMMU address translations and GPU shadow page table translations. This consolidation eliminates the need for separate shadow page table memory structures, thereby reducing overall memory usage while still supporting multiple VMs to share the physical GPU simultaneously.
Solution Approach 2:
The IOMMU translation cache is designed to perform multiple functions: it serves as both the address translation mechanism for IOMMU operations and as the shadow page table for GPU virtualization. This multi-functional approach allows a single data structure to fulfill multiple roles, reducing the total memory footprint required for supporting multiple virtual machines.
2Adaptability or versatility
If shadow page tables are implemented to support multiple VMs sharing a physical GPU, then multiple VMs can access the GPU simultaneously, but translation overhead increases
Solution Approach 1:
The IOMMU translation cache pre-computes and stores address translations in advance, so that when multiple VMs need to access the GPU, the translations are already available in cache rather than being computed on-demand. This preliminary action significantly reduces the translation overhead and latency when supporting multiple simultaneous VMs.
Solution Approach 2:
The patent uses the IOMMU translation cache to store pre-computed shadow page table entries, effectively copying the translation data into a high-speed cache structure. This allows rapid retrieval of translation information without repeatedly performing the full translation process, thereby reducing translation overhead for multiple VMs.
3Productivity
If GPU memory is shared among multiple VMs, then resource utilization improves, but performance bottlenecks occur due to memory access conflicts
Solution Approach 1:
The IOMMU translation cache acts as an intermediary layer between multiple VMs and the shared GPU memory resources. It manages and coordinates memory access translations for multiple VMs, reducing direct conflicts by providing a centralized translation mechanism that optimizes memory access patterns and minimizes bottlenecks when multiple VMs simultaneously access shared GPU memory.
Data Source
AI summary
An apparatus and method are described for allocating local memories to virtual machines. For example, one embodiment of an apparatus comprises: a command streamer to queue commands from a plurality of virtual machines (VMs) or applications, the commands to be distributed from the command streamer and executed by graphics processing resources of a graphics processing unit (GPU); a tile cache to store graphics data associated with the plurality of VMs or applications as the commands are executed by the graphics processing resources; and tile cache allocation hardware logic to allocate a first portion of the tile cache to a first VM or application and a second portion of the tile cache to a second VM or application; the tile cache allocation hardware logic to further allocate a first region in system memory to store spill-over data when the first portion of the tile cache and/or the second portion of the file cache becomes full.