Multicore GPU Tile Control List Stitching for Rendering Order

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Solution Overview

Problem

Implementing parallel rendering tasks on a multicore GPU while maintaining the correct order of primitives as specified by the application driver is challenging due to the unpredictable completion times of cores, which can lead to incorrect rendering if not managed properly.

Innovation Solution

A multicore graphics rendering system is designed with multiple cores configured for tile-based deferred rendering, where geometry processing cores produce tile control lists and fragment processing cores stitch these lists together in the correct order defined by group indices, allowing for efficient parallel processing without disrupting the sequence of rendering operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If rendering tasks are processed in parallel on multiple cores, then productivity is improved, but the correctness of rendering order deteriorates

Engineering Contradiction:
Improverendering throughputVSAvoidrendering order correctness
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The rendering pipeline is segmented into two independent stages: geometry processing stage (split into multiple geometry cores) and fragment processing stage (split into multiple fragment cores). Each stage processes work independently and writes to shared output buffers, allowing parallel execution while maintaining stage boundaries that preserve rendering order.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Shared output buffers act as intermediaries between geometry cores and fragment cores. Geometry cores write transformed geometry data to these buffers, and fragment cores read from them. This intermediary mechanism decouples the cores, allowing independent parallel execution while ensuring that all geometry processing completes before fragment processing begins for each draw call.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If central coordination is used to maintain rendering order, then reliability is improved, but device complexity increases

Engineering Contradiction:
Improverendering order correctnessVSAvoidcoordination overhead
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Each geometry core independently processes its assigned draw calls and writes results to shared output buffers. Each fragment core independently reads from these buffers and processes fragments. The system self-organizes through the buffer interface without requiring a central coordinator to manage task distribution or synchronization, reducing complexity while maintaining correctness.

Inventive Principle:
Principle #25Self-service

3Reliability

If all geometry is processed before fragment processing, then rendering order correctness is improved, but loss of time increases

Engineering Contradiction:
Improverendering order correctnessVSAvoidrendering latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

Geometry processing is performed as a preliminary action that completes entirely before fragment processing begins. By separating the pipeline into distinct stages where geometry processing must complete first, the system ensures rendering order correctness while allowing fragment processing to start immediately once geometry is ready, minimizing idle time.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20230334748A1Control stream stitching for multicore 3-d graphics rendering
Publication Date: 2023.10.19 IMAGINATION TECH LTD
  • US20230334748A1 patent drawing
  • US20230334748A1 patent drawing
  • US20230334748A1 patent drawing

AI summary

A multicore graphics rendering system includes a plurality of cores implementing tile-based deferred rendering of a stream of primitives. First cores perform geometry processing on groups of primitives. Each group of primitives is associated with a group index denoting its position in the stream of primitives. Each first core produces a set of tile control lists. Each tile control list produced by each first core describes the primitives processed by that first core that are present in the respective tile. Second cores perform fragment processing for one or more tiles. Each second core is configured to read, from a memory, the tile control lists produced for a given tile by the various first cores, and to stitch together these tile control lists to produce a combined tile control stream for the tile. The contents of the tile control lists are stitched together in the order defined by the group indices.