GPU Tiling Unit Early Depth Testing for Rendering Efficiency

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Solution Overview

Problem

As graphic resolution increases, existing graphics processing units (GPUs) face challenges in efficiently handling higher demands for performance, bandwidth, and memory, particularly in rendering three-dimensional objects into two-dimensional images, due to limitations in early depth testing and rendering order management.

Innovation Solution

A GPU architecture that includes a tiling unit and a rasterizer, which identifies representative primitives using depth values to perform early depth tests and determine visible primitives, allowing for optimized rendering by prioritizing rasterization based on a rendering order controlled by a sequencer, and utilizing coverage masks to manage visibility across tiles.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If early depth testing is performed on all primitives in rendering order, then rendering completeness is ensured, but computational efficiency deteriorates due to processing hidden primitives

Engineering Contradiction:
Improverendering efficiencyVSAvoidunnecessary computations
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The patent performs preliminary depth testing on primitive level before full rasterization. The tiling unit determines visible primitives by comparing depth values early in the pipeline, eliminating hidden primitives before they consume significant processing resources during fragment-level depth testing and rendering.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent segments the depth testing process into two distinct stages: primitive-level early depth testing in the tiling unit and fragment-level depth testing in the rasterizer. This segmentation allows early elimination of completely hidden primitives, reducing the workload for subsequent processing stages.

Inventive Principle:
Principle #1Segmentation

2Reliability

If all primitives are rasterized in rendering order, then rendering correctness is maintained, but memory bandwidth usage increases due to repeated tile processing

Engineering Contradiction:
Improverendering correctnessVSAvoidmemory bandwidth usage
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The tiling unit performs preliminary determination of visible primitives using depth value comparison before rasterization. This preliminary action creates an optimized primitive list that excludes hidden primitives, reducing the amount of data that needs to be stored and retrieved from memory during the rasterization phase.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent extracts and removes hidden primitives from the processing pipeline at the tiling stage. By identifying and eliminating primitives that will not contribute to the final image based on depth value comparison, the system reduces memory bandwidth requirements for storing and retrieving primitive data during rasterization.

Inventive Principle:
Principle #2Taking out (Extraction)

3Productivity

If representative primitives are determined using depth values, then visible primitive identification improves, but processing complexity increases at the tiling unit

Engineering Contradiction:
Improvevisible primitive identification accuracyVSAvoidtiling unit processing complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent changes the parameter used for primitive identification from spatial or rendering order parameters to depth value parameters. By using depth values as the primary criterion for determining representative primitives and visibility, the system achieves accurate hidden surface elimination while maintaining relatively simple processing logic in the tiling unit.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9741158B2Graphic processing unit and tile-based rendering method
Publication Date: 2017.08.22 SAMSUNG ELECTRONICS CO LTD
  • US9741158B2 patent drawing
  • US9741158B2 patent drawing
  • US9741158B2 patent drawing

AI summary

A graphics processing unit (GPU) is provided. The GPU includes a tiling unit and a rasterizer. The tiling unit is configured to determines primitives touching a corresponding tile in tiles in an image frame, to determine at least one representative primitive of the primitives using a depth value of each of the primitives, and to generate visible primitives of the primitives for the corresponding tile using a depth value of the at least one representative primitive. The rasterizer is configured to rasterize the at least one representative and the visible primitives.