GPU Tile Distribution Using Load-Aware Core Assignment
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Solution Overview
Problem
In traditional tile-based rendering architectures, workloads distributed to processor cores are unbalanced, leading to low overall rendering performance.
Innovation Solution
A method and apparatus for tile distribution in a graphics processing unit (GPU) that determines load levels for each tile and assigns them to processor cores based on state indicators, ensuring balanced load distribution by considering the number of primitives in each tile.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional tile-based rendering architecture is used, then power consumption is reduced and mobile devices can operate, but workload distribution to processor cores becomes unbalanced leading to low rendering performance
Solution Approach 1:
The patent applies preliminary action by calculating and determining the load level of each tile in advance during the frontend processing stage, before the actual rendering execution. This allows the backend to make informed distribution decisions without adding computational overhead during the critical rendering path, thus improving rendering performance while maintaining energy efficiency.
Solution Approach 2:
The patent implements feedback by using the determined load levels of tiles as input for the distribution algorithm that assigns tiles to processor cores. The system continuously monitors and adjusts tile distribution based on load level information, creating a closed-loop control mechanism that balances workload dynamically across cores, thereby improving rendering performance without increasing power consumption.
2Productivity
If tiles are distributed without considering load levels, then distribution process is simple, but workload becomes unbalanced across processor cores
Solution Approach 1:
The patent determines load levels for all tiles during the frontend processing stage before distribution occurs. This preliminary calculation of load levels provides the necessary information for balanced distribution without adding complexity to the actual distribution execution, as the heavy lifting of analysis is completed in advance.
Solution Approach 2:
The patent segments the tile distribution problem into two distinct phases: frontend load level determination and backend distribution execution. By separating the analytical phase (load assessment) from the execution phase (tile assignment), the system achieves workload balancing without complicating the distribution process itself, as each phase has a clear, focused function.
3Productivity
If load level calculation is performed for each tile, then workload balancing is achieved, but additional processing steps are required
Solution Approach 1:
The patent merges the load level calculation process with the existing frontend processing pipeline of the tile-based rendering architecture. By integrating load determination into the frontend's existing operations rather than adding a separate parallel process, the system achieves load balancing capability without significantly increasing processing steps or system complexity.
Solution Approach 2:
The patent performs load level calculation as a preliminary step within the existing processing flow, completing the analysis work before tiles need to be distributed. This approach achieves workload balancing while minimizing additional processing steps, as the load information is prepared in advance and can be used directly by the distribution algorithm without requiring repeated calculations.
Data Source
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AI summary
Disclosed in the embodiments of the present application are a tile distribution method and apparatus, and a device, a storage medium and a computer program product. The method comprises: determining, by means of a front-end portion of a TBR architecture, a load level corresponding to each tile among a plurality of tiles, wherein the load level is used for representing the number of primitives present in the tile; transmitting, to a rear-end portion of the TBR architecture, the load level corresponding to each tile; and for each tile, by means of the rear-end portion of the TBR architecture and on the basis of a state indicator, which corresponds to each processor core, in a state indicator group corresponding to the tile, determining, from among at least two processor cores, a target processor core corresponding to the tile, wherein the arrangement sequence of state indicators in the state indicator group corresponding to the tile is related to the load level of the tile.