GPU User-Mode Command Scheduling Without CPU Round Trips

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Solution Overview

Problem

Conventional processing systems experience unnecessary latency and bandwidth consumption due to CPU-GPU message exchanges, particularly in user mode operations, where the CPU controls command execution and DMA operations, leading to inefficiencies in graphics rendering and frame rate adjustments.

Innovation Solution

The GPU operates in user mode, scheduling commands without notifying the CPU, allowing it to execute additional commands based on context and state information, reducing latency and bandwidth by eliminating unnecessary message exchanges.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the CPU controls command execution and DMA operations in user mode, then system control and security are maintained, but latency and bandwidth consumption increase due to frequent CPU-GPU message exchanges

Engineering Contradiction:
Improvesystem controlVSAvoidlatency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent segments the command execution control between CPU and GPU: the CPU generates initial draw calls and commands, while the GPU autonomously executes additional commands (such as DMA operations) without requiring continuous CPU intervention. This segmentation allows the GPU to operate independently in user mode, reducing message exchange frequency and latency while maintaining overall system control through the initial CPU-generated command structure.

Inventive Principle:
Principle #1Segmentation

2Reliability

If the CPU generates all commands including DMA operations, then command accuracy and security are ensured, but processing speed and frame rates decrease due to CPU bottleneck

Engineering Contradiction:
Improvecommand accuracyVSAvoidprocessing speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The CPU performs preliminary action by generating the initial draw call and command structure with necessary context information before transferring control to the GPU. The GPU then uses this preliminary information to autonomously generate and execute additional commands (including DMA operations) without further CPU involvement, thereby maintaining command accuracy from the initial CPU setup while achieving higher processing speeds through GPU autonomy.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If the GPU executes additional commands autonomously in user mode, then processing efficiency and frame rates improve, but device complexity increases

Engineering Contradiction:
Improveframe rateVSAvoidGPU control logic
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The GPU is empowered with self-service capabilities in user mode, allowing it to autonomously execute additional commands (such as DMA operations and frame rate adjustments) based on the initial context provided by the CPU. This self-service approach eliminates the need for complex CPU-GPU communication protocols and external control logic, thereby improving frame rates while the increased complexity is contained within the GPU itself rather than the overall system architecture.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS20260111263A1Distributed user mode processing
Publication Date: 2026.04.23 ADVANCED MICRO DEVICES INC
  • US20260111263A1 patent drawing
  • US20260111263A1 patent drawing
  • US20260111263A1 patent drawing

AI summary

A first processing unit such as a graphics processing unit (GPU) pipelines that execute commands and a scheduler to schedule one or more first commands for execution by one or more of the pipelines. The one or more first commands are received from a user mode driver in a second processing unit such as a central processing unit (CPU). The scheduler schedules one or more second commands for execution in response to completing execution of the one or more first commands and without notifying the second processing unit. In some cases, the first processing unit includes a direct memory access (DMA) engine that writes blocks of information from the first processing unit to a memory. The one or more second commands program the DMA engine to write a block of information including results generated by executing the one or more first commands.