Variable Register Allocation for GPU Hardware Threads
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Solution Overview
Problem
Conventional graphics processor architectures have a fixed relationship between the number of registers that can be used by a hardware thread, which may not be optimal for specific workloads.
Innovation Solution
The implementation of a variable registers per thread (VRT) feature within a graphics processor, allowing for adjustment of the number of active hardware threads and registers per thread on a per-shader stage basis, tuned for specific workloads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a fixed relationship between number of registers and concurrent hardware threads is maintained, then architecture stability is preserved, but workload optimization capability deteriorates
Solution Approach 1:
The patent implements dynamic register allocation where the number of registers per hardware thread can be adjusted at runtime based on workload characteristics. The register allocation is no longer fixed but adapts to different execution contexts, allowing the system to optimize for either more threads or more registers per thread depending on the specific workload requirements.
Solution Approach 2:
The system changes the parameter of register allocation size dynamically. Different register allocation sizes (e.g., 32, 64, 128 registers per thread) can be selected and applied based on the detected workload type, transforming the static parameter into a dynamic one that responds to operational conditions.
2Productivity
If the number of concurrent hardware threads is increased, then processing throughput is improved, but register allocation flexibility deteriorates
Solution Approach 1:
The system dynamically adjusts the number of concurrent hardware threads and registers per thread based on workload demands. When workloads require more register space, the system can reduce the number of concurrent threads to allocate more registers per thread, and vice versa, maintaining flexibility while managing throughput.
Solution Approach 2:
The patent enables changing the operational parameters of thread count and register allocation size. The system can switch between different configuration modes (e.g., high-throughput mode with many threads and fewer registers, versus precision mode with fewer threads and more registers) to optimize for different performance metrics.
3Quantity of substance
If register file size is increased, then register availability is improved, but hardware resource utilization deteriorates
Solution Approach 1:
Instead of uniformly increasing register file size for all hardware threads, the patent applies local quality by allocating different register sizes to different threads based on their specific needs. Each thread can be configured with an appropriate register allocation size, avoiding the waste of allocating excessive registers to threads that don't need them.
Solution Approach 2:
The system changes the register allocation parameter dynamically rather than using a fixed large register file. By adjusting the register allocation size parameter based on actual workload requirements, the system maintains high register availability when needed while avoiding unnecessary hardware resource consumption during other operation modes.
Data Source
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AI summary
Described herein is a graphics processor having processing resources with configurable thread and register configurations. Program code can configure a number of registers and accumulators that will be used by hardware threads during execution of the program code by the graphics processor. Processing resources within the graphics processor can be configured to assign different numbers of registers and accumulators to hardware threads based on the configuration requested by program code to be executed by the processing resource.