GPU Wavefront Classification for Virtual Address Translation Latency
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Solution Overview
Problem
In processors that perform SIMD instructions, such as GPUs, virtual address translation latency is high due to the need for multiple translations and the pressure this puts on memory systems, especially when temporal locality of pages is difficult to capture with intermediate structures like page tables or TLBs, leading to delays and inefficiencies.
Innovation Solution
A system and method that classifies wavefronts into subsets based on classification criteria to reduce virtual address translation latency, using a wavefront classifier and scheduler to prioritize active subsets over pending ones, and potentially include a pre-fetch subset to manage address translations efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If virtual memory address translation is implemented in a SIMD processor, then memory management capability is improved, but translation latency increases significantly
Solution Approach 1:
The patent segments wavefronts into multiple subsets (first subset, second subset, third subset) based on their address translation needs and readiness states. This segmentation allows the system to process different subsets in parallel through different processing lanes, reducing overall translation latency by avoiding sequential processing of all wavefronts.
Solution Approach 2:
The patent performs preliminary classification of wavefronts into different subsets before processing. By identifying and separating wavefronts that are ready for execution from those requiring translation earlier, the system can prepare and pre-fetch translation data in advance, reducing the critical path latency during actual execution.
2Productivity
If multiple address translations are performed per instruction, then SIMD processing capability is improved, but pressure on memory system increases
Solution Approach 1:
The patent merges translation requests from multiple wavefronts into unified translation operations. By combining translation needs across different subsets and processing them through shared translation resources, the system reduces redundant memory accesses and consolidates memory system pressure, allowing SIMD processing capability to scale without linearly increasing memory subsystem stress.
3Productivity
If intermediate structure size is increased to capture temporal locality, then translation efficiency is improved, but device complexity increases
Solution Approach 1:
The patent implements dynamic wavefront scheduling where the classification and processing order of wavefront subsets changes based on real-time translation readiness and execution readiness. This dynamic approach allows the system to adapt to temporal locality patterns without requiring a statically large intermediate structure, as the scheduler can flexibly reorder processing to maximize cache hit rates with existing structure sizes.
Data Source
AI summary
Embodiments disclose a system and method for reducing virtual address translation latency in a wide execution engine that implements virtual memory. One example method describes a method comprising receiving a wavefront, classifying the wavefront into a subset based on classification criteria selected to reduce virtual address translation latency associated with a memory support structure, and scheduling the wavefront for processing based on the classifying.