Graded Channel NOR Flash Cells for Short-Channel CHEI Programming
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Solution Overview
Problem
NOR flash memory arrays face challenges in scaling down below 100 nm due to memory cell device punch-through issues and inefficiencies in Channel Hot Electron Injection (CHEI) programming schemes, which are not optimized for the N-type NVM devices with the minimum gate length=32 nm fabricated with 40 nm process technology provided by a foundry.
Innovation Solution
The solution involves the use of graded channel MOSFET devices with asymmetrically distributed impurity concentrations near the source regions 210 have very high electron injection rate to the storage material 280.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the gate length of memory cell devices is shortened below 100 nm to improve device performance and scaling, then device performance and fabrication cost are improved, but punch-through voltage drops below the required threshold causing programming failures
Solution Approach 1:
The patent applies different impurity concentrations at different locations within the channel region. Specifically, higher impurity concentrations are introduced near the source and drain regions while maintaining lower concentrations in the middle channel, creating a graded channel profile that locally optimizes both carrier injection and punch-through prevention
Solution Approach 2:
The patent changes the impurity concentration parameter along the channel length to create a graded channel. This parameter variation allows the channel to simultaneously support high electron injection rates near the source and maintain adequate punch-through voltage near the drain, resolving the contradiction between performance and reliability
2Ease of operation
If conventional CHEI programming scheme is used for short channel devices, then programming operation can be performed, but programming efficiency is insufficient for N-type NVM devices with gate length 32 nm
Solution Approach 1:
The graded channel structure creates favorable local conditions near the source region for electron acceleration and injection. The higher impurity concentration near the source enhances the electric field for carrier acceleration, while the gradient transitions smoothly to lower concentrations that facilitate efficient electron injection into the floating gate
Solution Approach 2:
The patent introduces asymmetric impurity distribution in the channel, with different concentration profiles near the source and drain regions. This asymmetry is specifically designed to optimize the programming process by creating favorable conditions for electron injection while maintaining device operation characteristics
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The graded channel MOSFET devices enhance ChiTel programming efficiency and improve short channel margins by increasing electron injection rates and reducing leakage currents, thereby enabling effective programming and operation in NOR flash memory arrays with gate lengths less than 100 nm.
Implementation Method 1
enhancing the ChiTel (Channel induced Ternary electron) programming efficiency
Implementation Method 2
improving short channel margins for the gate lengths of memory cell devices less than 100 nm
Data Source
AI summary
A NOR flash memory array is disclosed, comprising: multiple cells organized in rows and columns, each cell comprising a channel region, a charge storing material, a control gate, a source region and a drain region, the cells along a predefined direction being arranged in cell pairs such that each cell pair shares a common source region that is encircled by a source halo implant region. The source halo implant region has the same conductivity type as the substrate, and the source halo implant region has a higher impurity concentration than a drain side of the channel region. The invention enhances the ChiTel programming efficiency and improves the short channel margins for the gate lengths of memory cells less than 100 nm in NOR flash memory array.