Graded Dopant Profiles in Strained Transistor Source-Drain Regions
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The complexity of manufacturing sophisticated dopant profiles in transistors, particularly in the drain and source regions, due to the need for precise strain induction and dopant distribution to enhance charge carrier mobility and reduce series resistance, is challenging, especially as transistor dimensions shrink, leading to issues like short channel effects and increased dopant-induced stress relaxation.
Innovation Solution
A method involving selective epitaxial growth of a strain-inducing semiconductor alloy with a graded in situ dopant concentration, combined with implantation steps, to create complex vertical and lateral dopant profiles, allowing for reduced implantation energies and avoiding implantation-induced damage, thereby maintaining strain and improving dopant distribution without compromising channel region integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional implantation techniques are used to form dopant profiles in drain and source regions, then dopant distribution can be achieved, but implantation-induced damage and stress relaxation occur that compromise strain and channel region integrity
Solution Approach 1:
A sacrificial oxide layer is introduced as an intermediary medium between the ion implantation process and the semiconductor crystal structure. This oxide layer absorbs the implantation damage that would otherwise be inflicted on the drain/source regions and channel, allowing precise dopant profiling without compromising crystal integrity or strain. The oxide is subsequently removed, leaving the damaged layer behind while preserving the underlying semiconductor structure.
Solution Approach 2:
The sacrificial oxide layer is formed in advance before ion implantation, creating a protective buffer that pre-positioned damage absorption capability. This preliminary action enables subsequent implantation steps to proceed without directly damaging the semiconductor crystal or releasing stress that would relax the strain in the channel region.
2Speed
If transistor dimensions are continuously shrunk to increase operating speed, then channel length is reduced and operating speed increases, but short channel effects and dopant-induced stress relaxation are exacerbated
Solution Approach 1:
The sacrificial oxide layer serves as a mediator that decouples the implantation process from the semiconductor structure, enabling precise dopant profiling in scaled devices without inducing stress relaxation. This is critical for maintaining strain in short-channel transistors where stress control is paramount for reliability.
Solution Approach 2:
The invention applies different treatments to different regions: the sacrificial oxide is selectively formed and removed in drain/source regions to enable precise dopant profiling, while the channel region maintains its strain through protected implantation processes. This local differentiation allows independent optimization of dopant profiles and strain characteristics.
3Manufacturing precision
If sophisticated implantation techniques are used to achieve complex dopant profiles, then dopant distribution precision is improved, but process complexity increases
Solution Approach 1:
The sacrificial oxide layer is a simple, well-established material that can be formed using conventional oxidation processes. Its introduction adds minimal process complexity while enabling sophisticated dopant profiles through standard ion implantation techniques, avoiding the need for complex spacer and lithography sequences.
4Reliability
If high dopant concentration is used in drain and source regions to reduce series resistance, then conductivity is improved, but short channel effects and leakage current increase
Solution Approach 1:
The sacrificial oxide enables highly localized dopant profiling with precise vertical and lateral control. This allows creation of complex dopant structures such as lightly-doped drain extensions, heavily-doped contact regions, and graded profiles that simultaneously reduce series resistance in contact areas while maintaining lower doping near the channel to minimize short channel effects and leakage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process by reducing the number of complex spacer and lithography steps, enabling efficient formation of sophisticated drain and source regions with enhanced strain and dopant profiles, improving transistor performance while minimizing leakage currents and stress relaxation.
Implementation Method 1
a strain-inducing alloy, such as a silicon/germanium alloy, for creating strain in the channel region
Implementation Method 2
selective epitaxial growth of a strain-inducing semiconductor alloy with a graded in situ dopant concentration
Implementation Method 3
performing a heat treatment to form drain and source extension regions on the basis of the varying dopant concentration of the dopant species
Data Source
AI summary
The dopant profile of a transistor may be obtained on the basis of an in situ doped strain-inducing semiconductor alloy wherein a graded dopant concentration may be established along the height direction. Consequently, the semiconductor alloy may be positioned in close proximity to the channel region, thereby enhancing the overall strain-inducing efficiency, while not unduly compromising the finally obtained dopant profile. Furthermore, additional implant species may be incorporated prior to selectively growing the semiconductor alloy, thereby avoiding implantation-induced relaxation of the internal strain.