Graded Doping Reduces Rectifier Process Sensitivity
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Solution Overview
Problem
Electrode-semiconductor rectifiers exhibit significant variations in electrical characteristics across semiconductor wafers and between lots due to surface roughness caused by electrode formation processes, particularly the nickel silicide layer formation process.
Innovation Solution
Grading the net doping concentration in the semiconductor material adjacent to the electrode, with the concentration decreasing in value with distance from the electrode, effectively reducing surface roughness and variations in electrical properties. This is achieved by forming a graded region within a specific distance, such as a half-micron, to prevent the formation of an ohmic contact and enhance device uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If electrode formation processes (particularly nickel silicide layer formation) are used to create rectifiers, then the device can be manufactured with standard processes, but surface roughness increases causing large variations in electrical characteristics across wafers and between lots
Solution Approach 1:
The patent applies local quality by creating a graded doping region specifically adjacent to the electrode contact area, where the doping concentration varies spatially (higher near the electrode, lower further away). This localized modification of the semiconductor material properties at the critical electrode-semiconductor interface compensates for the surface roughness effects without requiring changes to the entire wafer or other regions, thus maintaining ease of manufacture while improving electrical characteristics uniformity
Solution Approach 2:
The patent changes the doping concentration parameter in the semiconductor material adjacent to the electrode, creating a graded profile where the net doping concentration decreases with distance from the electrode. This parameter change in the semiconductor material compensates for the surface roughness variations introduced by the nickel silicide formation process, reducing lot-to-lot and wafer-to-wafer variations in electrical characteristics while maintaining standard manufacturing processes
2Device complexity
If the net doping concentration is kept uniform in the semiconductor material, then the manufacturing process is simpler, but surface roughness from electrode formation causes significant variations in electrical properties
Solution Approach 1:
The patent introduces local quality by creating a non-uniform doping concentration profile specifically in the region adjacent to the electrode, while leaving other regions of the semiconductor material with uniform doping. This localized graded doping region addresses the reliability issue caused by surface roughness without significantly increasing overall device complexity, as the grading is confined to a specific area rather than the entire device structure
Solution Approach 2:
The patent modifies the doping concentration parameter in the semiconductor material to create a graded profile adjacent to the electrode, where concentration decreases with distance from the electrode surface. This parameter change improves electrical properties consistency by compensating for surface roughness effects, accepting increased device complexity in the form of a non-uniform doping profile only where necessary near the electrode interface
Data Source
AI summary
Disclosed are semiconductor devices and methods of making semiconductor devices. An exemplary embodiment comprises a semiconductor layer of a first conductivity type having a first surface, a second surface, and a graded net doping concentration of the first conductivity type within a portion of the semiconductor layer. The graded portion is located adjacent to the top surface of the semiconductor layer, and the graded net doping concentration therein decreasing in value with distance from the top surface of the semiconductor layer. The exemplary device also comprises an electrode disposed at the first surface of the semiconductor layer and adjacent to the graded portion.