Graded Edge Ring for Uniform Semiconductor Etching
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Solution Overview
Problem
As semiconductor devices undergo etching processes, the edge region of wafers often experiences uneven etching rates compared to the central region, leading to non-uniform etching profiles, which can affect the integration density and performance of electronic components.
Innovation Solution
The use of a graded edge ring with varying widths and materials that are not solid phase catalysts for etchant reactions, allowing for controlled etch rates between the edge and central regions of the wafer, thereby achieving a more uniform etching profile.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching processes are used without edge ring modifications, then the etching process is simple and fast, but the etching uniformity across the wafer deteriorates due to edge effects
Solution Approach 1:
The edge ring is designed with spatially varying properties: different widths at different radial positions and different material compositions (including regions with and without solid phase catalysts) to create localized control over etching rates at the wafer edge, directly addressing the edge effect problem while maintaining simplicity elsewhere
Solution Approach 2:
The edge ring parameters (width, material composition, catalyst presence) are systematically varied to control the etching rate at the wafer edge. By changing these parameters, the etching uniformity across the wafer is improved without requiring complete process redesign
2Productivity
If the minimum feature size is reduced to improve integration density, then more components can be integrated, but etching uniformity and process control deteriorate
Solution Approach 1:
The graded edge ring provides localized control over etching conditions specifically at the wafer edge, ensuring that even as feature sizes shrink and integration density increases, the etching uniformity is maintained through spatially tailored edge ring properties
Solution Approach 2:
The edge ring design allows for dynamic adjustment of etching rates at the wafer edge through its graded structure, enabling process optimization for smaller feature sizes while maintaining overall etching uniformity across the wafer surface
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the difference in etched height between the central and edge regions, enhancing the uniformity of the etching process and improving the integration density of electronic components, such as in FinFET manufacturing.
Implementation Method 1
the edge ring is graded to have different steps that have different heights and are coated with different materials. Grading the edge ring with different steps and materials allows a difference in etch rate between the edge and the center of the wafer to be controlled during etching
Data Source
AI summary
A semiconductor device, method, and tool of manufacture includes a semiconductor manufacturing tool. The semiconductor manufacturing tool includes push pins in a chuck and an edge ring over the chuck. The push pins are configured to hold a wafer, and are operable to vary a height of the wafer with respect to the chuck. The edge ring has a first width at a base proximate the chuck, and a second width at a point distal the chuck. The first width is greater than the second width. A distance from the wafer to the edge ring varies when the push pins vary the height of the wafer with respect to the chuck.