3D Memory Cell Stack with Graded Gate Thickness and Insulation Spacing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor devices face challenges in increasing data storage capacity and improving electrical properties and reliability, particularly in three-dimensional memory cell configurations.
Innovation Solution
The semiconductor device incorporates a memory cell region with vertically stacked gate electrodes and interlayer insulating layers, where each gate electrode and interlayer insulating layer has varying thicknesses, forming a stack structure that enhances electrical properties and reliability by optimizing the overlap and spacing of these components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If gate electrodes and interlayer insulating layers are stacked vertically in a memory cell region overlapping the peripheral circuit region, then data storage capacity is increased, but electrical properties and reliability deteriorate
Solution Approach 1:
The patent applies local quality by making the fourth gate electrode have a greater thickness than the third gate electrode, and making the second interlayer insulating layer have a greater thickness than the third interlayer insulating layer. This localized variation in thickness in specific regions (where memory cell regions overlap with peripheral circuit regions) improves electrical properties and reliability while maintaining high data storage capacity through the overall vertical stacking structure.
2Ease of manufacture
If gate electrodes are made with uniform thickness in the vertical stack, then manufacturing is simplified, but electrical properties deteriorate
Solution Approach 1:
Instead of uniform thickness throughout the stack, the patent implements local quality by selectively increasing the thickness of the fourth gate electrode and second interlayer insulating layer in specific positions. This allows optimization of electrical properties in critical regions while maintaining relatively simple manufacturing processes through controlled local variations rather than complex global restructuring.
Data Source
AI summary
A semiconductor device includes a peripheral circuit region and a memory cell region. The memory cell region may include a stack structure including gate electrodes and interlayer insulating layers repeatedly and alternately stacked in a vertical direction, and a channel structure penetrating through the stack structure. The gate electrodes may include first gate electrodes, second gate electrodes on the first gate electrodes, and third gate electrodes on the second gate electrodes. Each of the first gate electrodes may have a first thickness. Each of the second gate electrodes may have a second thickness that is greater than the first thickness. Each of the third gate electrodes may have a third thickness that is smaller than the second thickness.