Graded Grain Semiconductor Patterns in 3D Memory Stacks
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Solution Overview
Problem
Conventional semiconductor memory devices face limitations in integration density and manufacturing cost due to the difficulty in forming fine patterns, which restricts the advancement of memory device technology.
Innovation Solution
The development of three-dimensional memory devices with a stack of interleaved conductive and insulating patterns on a substrate, where a semiconductor pattern with a graded grain size distribution is used, achieved through partial laser annealing, allowing for improved integration density and reduced manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional planar semiconductor memory devices are used, then manufacturing process is simpler, but integration density is limited
Solution Approach 1:
The patent transitions from conventional two-dimensional planar memory structures to three-dimensional vertical structures by stacking multiple layers of conductive patterns and insulating patterns. The semiconductor pattern extends vertically through multiple data storage layers, enabling memory cells to be arranged in three dimensions rather than just on a flat plane, thereby significantly increasing integration density.
Solution Approach 2:
The patent implements a nested structure where semiconductor patterns are embedded within and pass through multiple stacked layers of conductive patterns and insulating patterns. Each layer is nested within the overall vertical structure, with the semiconductor pattern acting as a central core that connects multiple data storage layers, creating a compact nested architecture.
2Manufacturing precision
If finer patterns are produced to increase integration density, then device density improves, but manufacturing cost increases
Solution Approach 1:
The patent divides the semiconductor pattern into distinct regions with different grain sizes: a first region with a first mean grain size and a second region with a second mean grain size. This segmentation allows different portions of the same pattern to have optimized properties for different functions, enabling finer effective patterning without requiring proportionally more expensive manufacturing equipment across the entire structure.
Solution Approach 2:
The patent applies local quality by creating regions with different grain sizes within the semiconductor pattern. The first region has a first mean grain size optimized for certain electrical properties, while the second region has a second mean grain size optimized for other properties. This local differentiation allows the structure to achieve fine effective dimensions in critical areas without uniformly requiring expensive fine-patterning equipment throughout the entire device.
3Ease of manufacture
If uniform grain size is used in semiconductor pattern, then fabrication is simpler, but charge mobility is insufficient
Solution Approach 1:
The patent implements local quality by creating a graded grain size distribution within the semiconductor pattern. The first region has a first mean grain size that may be optimized for ease of fabrication and structural stability, while the second region has a second mean grain size that is optimized for enhanced charge mobility. This local differentiation allows the structure to achieve both fabrication feasibility and high charge mobility in different regions simultaneously.
Solution Approach 2:
The patent applies parameter changes by varying the grain size parameter throughout the semiconductor pattern. Instead of maintaining a uniform grain size, the patent creates a gradient where the mean grain size changes from the first region to the second region. This parameter variation enables optimization of charge mobility in regions where it is critical while maintaining structural integrity and ease of fabrication in other regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the integration density of memory devices while reducing production costs by enabling the formation of finer patterns and improving charge mobility through controlled grain size distribution in semiconductor patterns.
Implementation Method 1
A portion of the precursor semiconductor pattern is melted while leaving a portion of the precursor semiconductor pattern proximate the substrate in a solid state, e.g., by a partial laser annealing
Implementation Method 2
A portion of the precursor semiconductor pattern is melted while leaving a portion of the precursor semiconductor pattern proximate the substrate in a solid state
Implementation Method 3
The melted portion of the precursor semiconductor pattern is recrystallized. The recrystallizing may leave a semiconductor pattern in the opening having a graded grain size distribution
Data Source
AI summary
Memory devices include a stack of interleaved conductive patterns and insulating patterns disposed on a substrate. A semiconductor pattern passes through the stack of conductive patterns and insulating patterns to contact the substrate, the semiconductor pattern having a graded grain size distribution wherein a mean grain size in a first portion of the semiconductor pattern proximate the substrate is less than a mean grain size in a second portion of the semiconductor pattern further removed from the substrate. The graded grain size distribution may be achieved, for example, by partial laser annealing.